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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US10339043B1
System and method to match vectors using mask and count
Publication/Patent Number: US10339043B1 Publication Date: 2019-07-02 Application Number: 15/853,707 Filing Date: 2017-12-22 Inventor: Miller, Michael J   Assignee: MoSys, Inc.   IPC: H04L12/745 Abstract: An apparatus, system, and method is described for calculating a composite index into a customizable hybrid address space that is at least partially compressed to locate a longest prefix match (“LPM”) of a prefix string comprised of a plurality of multi-bit strides (“MBSs”). The device comprises: a mask-and-count logic for generating a base index into memory for a first MBS whose addresses are not compressed; a logical-shift apparatus that selectively uses a variable portion of the second MBS to generate an offset index from the given base index per an amount the second MBS addresses were actually compressed; and an add logic that adds the base index to the offset index to form the composite index that locates the LPM using a single access into memory. A compressed vector contains compression information of the second MBS in an information density format greater than a single bit to a single address.
2
US10320370B2
Methods and circuits for adjusting parameters of a transceiver
Publication/Patent Number: US10320370B2 Publication Date: 2019-06-11 Application Number: 13/728,910 Filing Date: 2012-12-27 Inventor: Choudhary, Prashant   Lin, Haidang   Wang, Alvin   Behtash, Saman   Desai, Shaishav   Assignee: MoSys, Inc.   IPC: H03K5/00 Abstract: Methods and circuits for analyzing a signal and adjusting parameters of an equalizer for a signal. The signal is received at a receiver over a channel wherein the signal has a wave form. The signal is equalized at an equalizer using an adjustable parameter for the equalization. Data points from the signal are sampled between upper and lower limits of a threshold at an error sampler. A performance metric of the signal is computed based on a statistical density of the data points from the signal between the upper and lower limits of the threshold.
3
US2019332274A1
PROCESSING ENGINES COUPLED WITH READ WRITE MODIFY MEMORY
Publication/Patent Number: US2019332274A1 Publication Date: 2019-10-31 Application Number: 16/174,268 Filing Date: 2018-10-29 Inventor: Miller, Michael J.   Patel, Jay B.   Morrison, Michael J.   Assignee: MoSys, Inc.   IPC: G06F3/06 Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.
4
US10050773B1
Bootstrapped autonegotiation clock from a referenceless clock chip
Publication/Patent Number: US10050773B1 Publication Date: 2018-08-14 Application Number: 15/199,979 Filing Date: 2016-06-30 Inventor: Boecker, Charles W   Irwin, Scott A   Assignee: MoSys, Inc.   IPC: H03L7/08 Abstract: A method, system and apparatus, for bootstrapping an autonegotiation signal in an intermediate device. The intermediate device initializes using a referenceless clock circuit. The intermediate device then recovers a more accurate clock sourced from a second device via a clock data recovery circuit in the intermediate device. The second device has a physical medium attachment interface within the intermediate device that does not require autonegotiation. The autonegotiation signal is communicated to a first device having a physical medium dependent interface to the intermediate device, thus requiring autonegotiation.
5
US10084488B1
Chip-to-chip port coherency without overhead
Publication/Patent Number: US10084488B1 Publication Date: 2018-09-25 Application Number: 15/199,982 Filing Date: 2016-06-30 Inventor: Irwin, Scott A   Jennings, Paul O.   Assignee: MoSys, Inc.   IPC: H04J3/04 Abstract: A network system includes a first device and a second device coupled to each other that mux and demux data for LSL to HSL transitions. The muxing and demuxing function in the first and second device, respectively, use timing logic from an existing training protocol, such as link training (“LT”). Although LT is used for establishing links between two chips, and has no provision for maintaining port coherency for port-specific input data on one chip to port-specific output data on another chip, the LT does have a uniquely identifiable logic transition in a known data pattern used for LT that can be multi-purposed for syncing the muxing and demuxing of the two interfaced chips, using a predetermined port sequence on both chips to maintain coherency of port-specific data.
6
US10114558B2
Integrated main memory and coprocessor with low latency
Publication/Patent Number: US10114558B2 Publication Date: 2018-10-30 Application Number: 15/898,659 Filing Date: 2018-02-18 Inventor: Miller, Michael J.   Patel, Jay B   Morrison, Michael J   Assignee: MOSYS, INC.   IPC: G06F3/06 Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.
7
US2018173433A1
Integrated Main Memory And Coprocessor With Low Latency
Publication/Patent Number: US2018173433A1 Publication Date: 2018-06-21 Application Number: 15/898,659 Filing Date: 2018-02-18 Inventor: Morrison, Michael J.   Patel, Jay B.   Miller, Michael J.   Assignee: MoSys, Inc.   IPC: H04L29/08 Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.
8
US9921755B2
Integrated main memory and coprocessor with low latency
Publication/Patent Number: US9921755B2 Publication Date: 2018-03-20 Application Number: 14/872,137 Filing Date: 2015-09-30 Inventor: Morrison, Michael J   Patel, Jay B   Miller, Michael J   Assignee: MoSys, Inc.   IPC: G06F12/0895 Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines that process on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.
9
US9971567B2
Method and apparatus for randomizer
Publication/Patent Number: US9971567B2 Publication Date: 2018-05-15 Application Number: 15/390,715 Filing Date: 2016-12-26 Inventor: Patel, Jay B   Morrison, Michael J.   Miller, Michael J.   Assignee: MoSys, Inc.   IPC: G06F7/58 Abstract: The randomizer includes connection circuitry with a random connection layout to parallely couple each of a quantity of bits for each of a plurality of inputs of bit width n to multiple output bits of a respectively coupled output. Combinational circuitry combines at least a portion of each of the plurality of outputs associated with each of the plurality of inputs to create a single resultant output of random data having a bit width of the quantity n.
10
EP2522017B1
MEMORY DEVICE INCLUDING A MEMORY BLOCK HAVING A FIXED LATENCY DATA OUTPUT
Publication/Patent Number: EP2522017B1 Publication Date: 2017-05-31 Application Number: 11742676.7 Filing Date: 2011-02-08 Inventor: Sikdar, Dipak   Assignee: Mosys, Inc.   IPC: G11C7/10
11
US9553566B2
Hybrid driver circuit
Publication/Patent Number: US9553566B2 Publication Date: 2017-01-24 Application Number: 14/564,618 Filing Date: 2014-12-09 Inventor: Groen, Eric D.   Boecker, Charles W.   Assignee: MoSys, Inc.   IPC: H03K3/012 Abstract: In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal. In this embodiment, the voltage mode driver circuit includes a current mode emphasis driver configured to selectively couple one of the first differential output terminal or the second differential output terminal to a first set of one or more current supplies and a different one of the first differential output terminal or second differential output terminal to a second set of one or more current supplies, based on one or more emphasis signals.
12
US2017109135A1
Method and Apparatus for Randomizer
Publication/Patent Number: US2017109135A1 Publication Date: 2017-04-20 Application Number: 15/390,715 Filing Date: 2016-12-26 Inventor: Miller, Michael J.   Morrison, Michael J.   Patel, Jay B.   Assignee: MoSys, Inc.   IPC: G06F7/58 Abstract: A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output.
13
EP2506149B1
Memory system including variable write command scheduling
Publication/Patent Number: EP2506149B1 Publication Date: 2017-08-09 Application Number: 12162499.3 Filing Date: 2012-03-30 Inventor: Morrison, Michael   Patel, Jay   Assignee: MoSys, Inc.   IPC: G06F13/42 Abstract: A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.
14
US9667546B2
Programmable partitionable counter
Publication/Patent Number: US9667546B2 Publication Date: 2017-05-30 Application Number: 13/912,033 Filing Date: 2013-06-06 Inventor: Morrison, Michael   Patel, Jay   Tang, Man Kit   Assignee: MoSys, Inc.   IPC: H04L12/801 Abstract: An integrated circuit device for receiving packets. The integrated circuit device includes a programmable partitionable counter that includes a first counter partition for counting a number of the packets, and a second counter partition for counting bytes of the packets. The first counter partition and the second counter partition are configured to be incremented by a single command from the packet processor.
15
EP2529307B1
HIERARCHICAL ORGANIZATION OF LARGE MEMORY BLOCKS
Publication/Patent Number: EP2529307B1 Publication Date: 2017-08-30 Application Number: 11737561.8 Filing Date: 2011-01-26 Inventor: Roy, Richard   Assignee: Mosys, Inc.   IPC: G11C11/4097
16
KR101600131B1
MEMORY SYSTEM INCLUDING VARIABLE WRITE COMMAND SCHEDULING
Publication/Patent Number: KR101600131B1 Publication Date: 2016-03-14 Application Number: 20120033541 Filing Date: 2012-03-30 Inventor: Morrison, Michael J   Patel, Jay B   Assignee: MOSYS, INC.   IPC: G06F9/30 Abstract: PURPOSE: A memory system including a variable write command scheduling is provided to perform memory command scheduling of a memory interface and to efficiently use usable bandwidth during memory transceiving. CONSTITUTION: A memory device(20) includes one or more memory arrays for storing data. A controller(22) is combined with the memory device. The controller responds reception of memory transaction through a memory interface. The controller reads out the data in one or more memory array. The memory transaction includes plural memory write command types. [Reference numerals] (15) Memory sub system; (20) Memory device; (22) Controller; (23) Storage device; (24) Processing; (25) Memory controller; (27) Router; (33A) Serial; (33B) Parallel; (50) ASIC/host; (AA) Memory transaction; (BB) Memory request
17
US2016164498A1
HYBRID DRIVER CIRCUIT
Publication/Patent Number: US2016164498A1 Publication Date: 2016-06-09 Application Number: 14/564,618 Filing Date: 2014-12-09 Inventor: Groen, Eric D.   Boecker, Charles W.   Assignee: MoSys, Inc.   IPC: H03K3/012 Abstract: In one embodiment, a voltage mode driver circuit includes a first voltage adjusting circuit configured to provide an adjustable first pseudo-supply voltage to a first node based on a first supply voltage, including generating the first pseudo-supply voltage based on a first reference voltage and feedback from the first node. In this embodiment, the voltage mode driver circuit includes switching circuitry configured to selectively couple one of the first node or a second node to a first differential output terminal and a different one of the first node or the second node to a second differential output terminal based on a data signal. In this embodiment, the voltage mode driver circuit includes a current mode emphasis driver configured to selectively couple one of the first differential output terminal or the second differential output terminal to a first set of one or more current supplies and a different one of the first differential output terminal or second differential output terminal to a second set of one or more current supplies, based on one or more emphasis signals.
18
US9361196B2
Memory device with background built-in self-repair using background built-in self-testing
Publication/Patent Number: US9361196B2 Publication Date: 2016-06-07 Application Number: 14/320,632 Filing Date: 2014-06-30 Inventor: Kleveland, Bendik   Sikdar, Dipak K   Chopra, Rajesh   Patel, Jay   Assignee: MoSys, Inc.   IPC: G06F11/20 Abstract: A memory device with a background built-in self-repair module (BBISRM) includes a main memory, an arbiter, and a redundant memory to repair a target memory under test (TMUT). The memory device also includes a background built-in self-test module (BBISTM) to identify portions of memory needing background built-in self-repair (BBISR). The BBISRM or the BBISTM can operate simultaneously while the memory device is operational for performing external accesses during field operation. The BBISR can detect and correct a single data bit error in the data stored in the TMUT. The arbiter configured to receive a read or write access memory request including a memory address, to determine if the memory address of the read or write access memory request matches the memory address mapped to the selected portion of the redundant memory, and to read or write data from the selected portion of the redundant memory, respectively.
19
US9342471B2
High utilization multi-partitioned serial memory
Publication/Patent Number: US9342471B2 Publication Date: 2016-05-17 Application Number: 12/697,141 Filing Date: 2010-01-29 Inventor: Miller, Michael J.   Roy, Richard S.   Assignee: MoSys, Inc.   IPC: G06F12/00 Abstract: A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are deserialized on the memory device, and are provided to a memory controller. The memory controller initiates accesses to a memory core in response to the received instructions. The memory core includes a plurality of memory partitions, which are accessed in a cyclic and overlapping manner. This allows each memory partition to operate at a slower frequency than the serial links, while properly servicing the received instructions. Accesses to the memory device are performed in a synchronous manner, wherein each access exhibits a known fixed latency.
20
TWI563516B
High utilization multi-partitioned serial memory
Publication/Patent Number: TWI563516B Publication Date: 2016-12-21 Application Number: 99145510 Filing Date: 2010-12-23 Inventor: Miller, Michael J   Roy, Richard S   Assignee: MOSYS, INC.   IPC: G11C7/10 Abstract: A memory device that includes an input interface that receives instructions and input data on a first plurality of serial links. The instructions and input data are de-serialized on the memory device
Total 14 pages