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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1 US2020111752A1
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2020111752A1 Publication Date: 2020-04-09 Application Number: 16/154,490 Filing Date: 2018-10-08 Inventor: Chen, Jenchun   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/552 Abstract: A semiconductor package including a substrate having a surface, and a conductive element on the first surface and electrically coupled to the substrate. The conductive element has a principal axis forming an angle less than 90 degrees with the surface.
2 US2020083132A1
SEMICONDUCTOR DEVICE PACKAGE
Publication/Patent Number: US2020083132A1 Publication Date: 2020-03-12 Application Number: 16/409,665 Filing Date: 2019-05-10 Inventor: Huang, Yen-chi   Hsieh, Hao-chih   Shih, Jin Han   Yeh, Yung I.   Pi, Tun-ching   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/31 Abstract: A semiconductor device package includes a carrier and an encapsulant disposed on the carrier. At least one portion of the encapsulant is spaced from the carrier by a space.
3 US2020075540A1
SUBSTRATE PANEL STRUCTURE AND MANUFACTURING PROCESS
Publication/Patent Number: US2020075540A1 Publication Date: 2020-03-05 Application Number: 16/118,235 Filing Date: 2018-08-30 Inventor: Lu, Wen-long   Fang, Jen-kuang   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/00 Abstract: A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.
4 US2020118912A1
SEMICONDUCTOR DEVICE PACKAGE, ELECTRONIC ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: US2020118912A1 Publication Date: 2020-04-16 Application Number: 16/264,602 Filing Date: 2019-01-31 Inventor: Ho, Cheng-lin   Lee, Chih-cheng   Chen, Chun Chen   Chen, Chen Yuang   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/498 Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
5 US2020083143A1
ELECTRONIC DEVICE
Publication/Patent Number: US2020083143A1 Publication Date: 2020-03-12 Application Number: 16/566,502 Filing Date: 2019-09-10 Inventor: Tsai, Jung-che   Hu, Ian   Hung, Chih-pin   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/427 Abstract: An electronic device includes a main substrate, a semiconductor package structure and at least one heat pipe. The semiconductor package structure is electrically connected to the main substrate, and includes a die mounting portion, a semiconductor die and a cover structure. The semiconductor die is disposed on the die mounting portion. The cover structure covers the semiconductor die. The heat pipe contacts the cover structure for dissipating a heat generated by the semiconductor die.
6 US2020080841A1
OPTICAL MODULE AND METHOD OF MAKING THE SAME
Publication/Patent Number: US2020080841A1 Publication Date: 2020-03-12 Application Number: 16/683,117 Filing Date: 2019-11-13 Inventor: Chen, Ying-chung   Chan, Hsun-wei   Lai, Lu-ming   Chen, Kuang-hsiung   Assignee: Advanced semiconductor engineering inc   IPC: G01C3/08 Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.
7 US2020194327A1
SEMICONDUCTOR DEVICE PACKAGE
Publication/Patent Number: US2020194327A1 Publication Date: 2020-06-18 Application Number: 16/802,468 Filing Date: 2020-02-26 Inventor: Chiu, Chi-tsung   Wang, Meng-jen   Chuang, Cheng-hsi   Hsieh, Hui-ying   Lee, Hui Hua   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/31 Abstract: A semiconductor device package includes: (1) a conductive base comprising a sidewall, a cavity defined from a first surface of the conductive base, the cavity having a bottom surface and a depth; (2) a semiconductor die disposed on the bottom surface of the cavity, the semiconductor die having a first surface and a second surface opposite the first surface, the second surface of the semiconductor die bonded to the bottom surface of the cavity; and (3) a first insulating material covering the sidewall of the conductive base and extending to a bottom surface of the conductive base.
8 US2020126881A1
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2020126881A1 Publication Date: 2020-04-23 Application Number: 16/592,543 Filing Date: 2019-10-03 Inventor: Liao, Guo-cheng   Ding, Yi Chuan   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/31 Abstract: A package substrate includes a first dielectric layer, a first patterned conductive layer and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks of the first set of alignment marks and the first edge are different from each other.
9 US2020259058A1
SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2020259058A1 Publication Date: 2020-08-13 Application Number: 16/862,447 Filing Date: 2020-04-29 Inventor: Wu, Mei-yi   Lai, Lu-ming   Lee, Yu-ying   Chang, Yung-yi   Assignee: Advanced semiconductor engineering inc   IPC: H01L33/62 Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.
10 US202002162A1
SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME
Publication/Patent Number: US202002162A1 Publication Date: 2020-01-02 Application Number: 20/191,645 Filing Date: 2019-06-25 Inventor: Lai, Lu-ming   Tsai, Yu-hsuan   Tseng, Chi Sheng   Chen, Yin-hao   Wu, Hsin Lin   Yu, San-kuei   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/498 Abstract: A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.
11 US2020275030A1
OPTICAL MEASUREMENT EQUIPMENT AND METHOD FOR MEASURING WARPAGE OF A WORKPIECE
Publication/Patent Number: US2020275030A1 Publication Date: 2020-08-27 Application Number: 16/285,000 Filing Date: 2019-02-25 Inventor: Wang, Ming-han   Hu, Ian   Shih, Meng-kai   Chen, Hsuan Yu   Assignee: Advanced semiconductor engineering inc   IPC: H04N5/232 Abstract: An optical measurement equipment includes an adjustment apparatus and at least two image capturing devices. The image capturing devices have a depth-of-field and attached to the adjustment apparatus. The image capturing devices are adjusted by the adjustment apparatus such that a portion to be measured of a workpiece is located within the depth-of-field of the image capturing devices.
12 US2020279788A1
SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE, AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2020279788A1 Publication Date: 2020-09-03 Application Number: 16/878,475 Filing Date: 2020-05-19 Inventor: Ho, Cheng-lin   Lee, Chih-cheng   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/367 Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.
13 US2020312733A1
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: US2020312733A1 Publication Date: 2020-10-01 Application Number: 16/370,633 Filing Date: 2019-03-29 Inventor: Yeh, Chang-lin   Kao, Jen-chieh   Chen, Sheng-yu   Chen, Yu-chang   Chen, Yu-chang   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/31 Abstract: A semiconductor package structure includes a substrate having a first surface and a second surface opposite to the first surface; a first encapsulant disposed on the first surface of the substrate, and defining a cavity having a sidewall, wherein an accommodating space is defined by the sidewall of the cavity of the first encapsulant and the substrate, and the accommodating space has a volume capacity; and a connecting element disposed adjacent to the first surface of the substrate and in the cavity, wherein a volume of the connecting element is substantially equal to the volume capacity of the accommodating space.
14 US2020279815A1
WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: US2020279815A1 Publication Date: 2020-09-03 Application Number: 16/289,072 Filing Date: 2019-02-28 Inventor: Huang, Wen Hung   Chung, Yan Wen   Cho, Huei-shyong   Assignee: Advanced semiconductor engineering inc   IPC: H01L23/00 Abstract: A wiring structure includes a conductive structure, a surface structure and at least one through via. The conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The surface structure is disposed adjacent to a top surface of the conductive structure. The through via extends through the surface structure and extending into at least a portion of the conductive structure.