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1
US2021005665A1
SPLIT PILLAR ARCHITECTURES FOR MEMORY DEVICES
Publication/Patent Number: US2021005665A1 Publication Date: 2021-01-07 Application Number: 16/460,875 Filing Date: 2019-07-02 Inventor: Fantini, Paolo   Pellizzer, Fabio   Fratin, Lorenzo   Assignee: Micron technology inc   IPC: H01L27/24 Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.
2
US10886918B2
Systems and methods for impedance calibration of a semiconductor device
Publication/Patent Number: US10886918B2 Publication Date: 2021-01-05 Application Number: 16/397,797 Filing Date: 2019-04-29 Inventor: Johnson, Jason M.   Assignee: Micron technology inc   IPC: H03K19/00 Abstract: Systems and methods for performing an efficient ZQ calibration are provided herein. The described techniques use non-linearity compensation circuitry configured to compensate for a non-linear relationship between variation in a plurality of ZQ calibration codes and corresponding resistance variations, by adjusting either: a magnitude of the adjustment to the calibration step, the ZQCODE to an alternative ZQCODE, or both the magnitude of the adjustment to the calibration step and the ZQCODE to the alternative ZQCODE.
3
US10883710B2
Solid state lights with cooling structures
Publication/Patent Number: US10883710B2 Publication Date: 2021-01-05 Application Number: 16/416,237 Filing Date: 2019-05-19 Inventor: Sills, Scott E.   Assignee: Micron technology inc   IPC: F21V29/00 Abstract: A solid state lighting (SSL) with a solid state emitter (SSE) having thermally conductive projections extending into an air channel, and methods of making and using such SSLs. The thermally conductive projections can be fins, posts, or other structures configured to transfer heat into a fluid medium, such as air. The projections can be electrical contacts between the SSE and a power source. The air channel can be oriented generally vertically such that air in the channel warmed by the SSE flows upward through the channel.
4
US10885945B2
Apparatus and methods to perform read-while write (RWW) operations
Publication/Patent Number: US10885945B2 Publication Date: 2021-01-05 Application Number: 15/688,667 Filing Date: 2017-08-28 Inventor: Barkley, Gerald John   Vimercati, Daniele   Garofalo, Pierguido   Assignee: Micron technology inc   IPC: G11C5/02 Abstract: A plurality of block configurations may be employed for read while write operations. In one apparatus example, a plurality of block configurations may be employed. Block configurations may include an arrangement of similarly doped semiconductor switches. Block configurations may select a respective tile of a memory array, a particular memory cell of the respective tile, and select a memory operation to apply to the particular memory cell. Immediately adjacent block configurations within a particular slice of the memory array may be substantially mirrored and immediately adjacent block configurations in separate immediately adjacent slices of the memory array may be substantially similar. Similarly doped diffusion regions for similarly doped semiconductor switches in substantially mirrored block configurations may be arranged to electrically share a common potential signal value level. Other apparatus and methods are also disclosed.
5
US10886244B2
Collars for under-bump metal structures and associated systems and methods
Publication/Patent Number: US10886244B2 Publication Date: 2021-01-05 Application Number: 15/684,054 Filing Date: 2017-08-23 Inventor: Mariottini, Giorgio   Vadhavkar, Sameer   Huang, Wayne   Chandolu, Anilkumar   Bossier, Mark   Assignee: Micron technology inc   IPC: H01L23/00 Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.
6
US10884647B2
UFS based idle time garbage collection management
Publication/Patent Number: US10884647B2 Publication Date: 2021-01-05 Application Number: 16/291,877 Filing Date: 2019-03-04 Inventor: Tanpairoj, Kulachet   Huang, Jianmin   Muchherla, Kishore Kumar   Assignee: Micron technology inc   IPC: G06F3/00 Abstract: Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules that are evaluated using the state of the NAND device. In some examples, the SLC cache migration process may utilize a number of NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data.
7
US2021005611A1
Integrated Assemblies Comprising Voids Between Active Regions and Conductive Shield Plates, and Methods of Forming Integrated Assemblies
Publication/Patent Number: US2021005611A1 Publication Date: 2021-01-07 Application Number: 16/502,584 Filing Date: 2019-07-03 Inventor: Sukekawa, Mitsunari   Taketani, Hiroaki   Assignee: Micron technology inc   IPC: H01L27/108 Abstract: Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies.
8
US10885977B2
Converged structure supporting buffering of recent writes and overwrite disturb remediation
Publication/Patent Number: US10885977B2 Publication Date: 2021-01-05 Application Number: 16/460,538 Filing Date: 2019-07-02 Inventor: Bradshaw, Samuel E.   Assignee: Micron technology inc   IPC: G11C13/00 Abstract: A computer-implemented method for remediating disruptions to memory cells is described. The method includes writing user data to an aggressor memory cell and determining a write timestamp and an overwrite count associated with the aggressor memory cell. The write timestamp indicates a last write to the aggressor memory cell and the overwrite count indicates the number of writes to the aggressor memory cell during a time period. Based on the write timestamp and the overwrite count, an increment value is determined for use with a disturb counter associated with a neighbor memory cell of the aggressor memory cell. In particular, the determined increment value is used, in response to the write, to increment the disturb counter associated with the neighbor memory cell. When the disturb counter is greater than or equal to a disturb threshold, remediation for the neighbor memory cell is performed.
9
US2021005259A1
Memory Cells, Memory Cell Programming Methods, Memory Cell Reading Methods, Memory Cell Operating Methods, and Memory Devices
Publication/Patent Number: US2021005259A1 Publication Date: 2021-01-07 Application Number: 17/031,454 Filing Date: 2020-09-24 Inventor: Liu, Jun   Assignee: Micron technology inc   IPC: G11C13/00 Abstract: Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In one embodiment, a memory cell includes a wordline, a first bitline, a second bitline, and a memory element. The memory element is electrically connected to the wordline and selectively electrically connected to the first bitline and the second bitline. The memory element stores information via a resistive state of the memory element. The memory cell is configured to convey the resistive state of the memory element via either a first current flowing from the first bitline through the memory element to the wordline or a second current flowing from the wordline through the memory element to the second bitline.
10
US2021005229A1
MEMORY WITH CONFIGURABLE DIE POWERUP DELAY
Publication/Patent Number: US2021005229A1 Publication Date: 2021-01-07 Application Number: 16/502,571 Filing Date: 2019-07-03 Inventor: Hiscock, Dale H.   Kaminski, Michael   Alzheimer, Joshua E.   Gentry, John H.   Assignee: Micron technology inc   IPC: G11C5/14 Abstract: Memory devices and systems with configurable die powerup delay, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die has a powerup group terminal and powerup group detect circuitry. The powerup group detect circuitry is configured to detect a powerup group assigned to the at least one memory die. The at least one memory die is configured to delay its powerup operation by a time delay corresponding to the powerup group to which it is assigned. In this manner, powerup operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.
11
US10884659B2
Host timeout avoidance in a memory device
Publication/Patent Number: US10884659B2 Publication Date: 2021-01-05 Application Number: 16/023,177 Filing Date: 2018-06-29 Inventor: Grosz, Nadav   Palmer, David Aaron   Assignee: Micron technology inc   IPC: G06F3/06 Abstract: Devices and techniques for host timeout avoidance in a memory device are disclosed herein. A memory device command is received with a memory device from a host. A determination is made, with the memory device, of a host timeout interval associated with the received memory device command. A timer of the memory device is initialized to monitor a time interval from receipt of the memory device command. After partially performing the memory device command, a response to the host before the memory device timer interval reaches the host timeout interval is generated by the memory device.
12
US10885987B2
Reading even data lines or odd data lines coupled to memory cell strings
Publication/Patent Number: US10885987B2 Publication Date: 2021-01-05 Application Number: 16/226,713 Filing Date: 2018-12-20 Inventor: Moschiano, Violante   D'alessandro, Andrea   Vali, Tommaso   Santin, Giovanni   Assignee: Micron technology inc   IPC: G11C16/26 Abstract: A method for reading an array of memory cells includes enabling a current to flow through even data lines of the array of memory cells. The method includes blocking a current from flowing through odd data lines of the array of memory cells. The method includes sensing data stored in memory cells coupled to the even data lines.
13
US10886445B2
Vertical solid-state transducers having backside terminals and associated systems and methods
Publication/Patent Number: US10886445B2 Publication Date: 2021-01-05 Application Number: 16/447,487 Filing Date: 2019-06-20 Inventor: Odnoblyudov, Vladimir   Schubert, Martin F.   Assignee: Micron technology inc   IPC: H01L21/00 Abstract: Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.
14
US10885998B1
Differential fuse-readout circuit for electronic devices
Publication/Patent Number: US10885998B1 Publication Date: 2021-01-05 Application Number: 16/681,413 Filing Date: 2019-11-12 Inventor: Chu, Wei Lu   Pan, Dong   Assignee: Micron technology inc   IPC: G11C17/18 Abstract: A circuit may include a voltage line and latch circuitry. The latch circuitry may be characterized by a switching voltage threshold and may be coupled to the voltage line. The latch circuitry may generate an output used to determine a state of a fuse. The circuit may also include generation circuitry coupled to the latch circuitry via the voltage line, wherein the generation circuitry is configured to pre-charge the voltage line to a first voltage between a system logical low voltage and the switching voltage threshold.
15
US10885964B2
Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory
Publication/Patent Number: US10885964B2 Publication Date: 2021-01-05 Application Number: 16/569,646 Filing Date: 2019-09-12 Inventor: Derner, Scott J.   Kawamura, Christopher J.   Assignee: Micron technology inc   IPC: G11C11/22 Abstract: Apparatuses and methods are disclosed that include ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.
16
US10885955B2
Driver circuit equipped with power gating circuit
Publication/Patent Number: US10885955B2 Publication Date: 2021-01-05 Application Number: 16/374,613 Filing Date: 2019-04-03 Inventor: Kojima, Mieko   Assignee: Micron technology inc   IPC: G11C7/10 Abstract: Disclosed herein is an apparatus that includes a rust buffer circuit, a plurality of first driver circuits configured to drive the first buffer circuit, and a plurality of first switch circuits configured to supply an operation voltage to the first driver circuits, respectively. The first driver circuits are collectively arranged in a first region in a matrix, and the first switch circuits are collectively arranged in a second region different from the first region.
17
US10886121B2
Methods of reducing silicon consumption, methods of forming a semiconductor structure, and methods of forming isolation structures
Publication/Patent Number: US10886121B2 Publication Date: 2021-01-05 Application Number: 16/425,045 Filing Date: 2019-05-29 Inventor: Sandhu, Gurtej S.   Assignee: Micron technology inc   IPC: H01L21/02 Abstract: A method of reducing silicon consumption of a silicon material. The method comprises cleaning a silicon material and subjecting the cleaned silicon material to a vacuum anneal at a temperature below a melting point of silicon and under vacuum conditions. The silicon material is subjected to additional process acts without substantially removing silicon of the silicon material. Additional methods of forming a semiconductor structure and forming isolation structures are also disclosed.
18
US10886998B2
Mixing coefficient data specific to a processing mode selection using layers of multiplication/accumulation units for wireless communication
Publication/Patent Number: US10886998B2 Publication Date: 2021-01-05 Application Number: 16/282,916 Filing Date: 2019-02-22 Inventor: Luo, Fa-long   Cummins, Jaime   Schmitz, Tamara   Chritz, Jeremy   Assignee: Micron technology inc   IPC: H04W4/00 Abstract: Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. The input data is mixed with coefficient data at layers of multiplication/accumulation processing units (MAC units). The processing mode selection may be associated with an aspect of a wireless protocol. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner.
19
US2021005257A1
TECHNIQUES FOR PROGRAMMING A MEMORY CELL
Publication/Patent Number: US2021005257A1 Publication Date: 2021-01-07 Application Number: 17/024,248 Filing Date: 2020-09-17 Inventor: Castro, Hernan A.   Tortorelli, Innocenzo   Pirovano, Agostino   Pellizzer, Fabio   Assignee: Micron technology inc   IPC: G11C13/00 Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
20
US2021005250A1
NEURAL NETWORK MEMORY
Publication/Patent Number: US2021005250A1 Publication Date: 2021-01-07 Application Number: 16/502,978 Filing Date: 2019-07-03 Inventor: Tortorelli, Innocenzo   Assignee: Micron technology inc   IPC: G11C11/54 Abstract: In an example, an apparatus can include an array of variable resistance memory cells and a neural memory controller coupled to the array of variable resistance memory cells and configured to apply a sub-threshold voltage pulse to a variable resistance memory cell of the array to change a threshold voltage of the variable resistance memory cell in an analog fashion from a voltage associated with a reset state to effectuate a first synaptic weight change; and apply additional sub-threshold voltage pulses to the variable resistance memory cell to effectuate each subsequent synaptic weight change.