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1
TW201928689A
Hardware controlling system and hardware controlling method
Publication/Patent Number: TW201928689A Publication Date: 2019-07-16 Application Number: 106144975 Filing Date: 2017-12-21 Inventor: Huang, Chien-hsing   Assignee: MStar Semiconductor, Inc   IPC: G06F13/10 Abstract: A hardware controlling system and a hardware controlling method are provided. The hardware controlling system is used for controlling a function circuit. The hardware controlling system includes a first transforming circuit, a second transforming circuit and an analyzing circuit. The first transforming circuit is used for transforming an instruction received from an operation system to be an intermediate physical address. The second transforming circuit is used for transforming the intermediate physical address to be a permission physical address which is consisted of a hardware physical address and a permission value according to an identification code of the operation system. The analyzing circuit is used for analyzing the permission physical address to obtain the hardware physical address and the permission value and determines a controlling value corresponding to the hardware physical address according to the permission value. The controlling value is used for permitting the operation system to control the function circuit.
2
TW201918876A
Multi-processor system and processor managing method thereof
Publication/Patent Number: TW201918876A Publication Date: 2019-05-16 Application Number: 106138347 Filing Date: 2017-11-06 Inventor: Huang, Chien-hsing   Assignee: MStar Semiconductor, Inc   IPC: G06F9/30 Abstract: A multi-processor system including plural processors, a register, a thread generating circuit, a flag determining circuit, a scheduler, an adjusting circuit, and an interrupt controller is provided. The acceptance for a shared peripheral interrupt of a specific processor is recorded in the register. The thread generating circuit receives requests and accordingly generates threads to be executed by the processors. Whenever the thread generating circuit receives one request, the flag determining circuit determines a real-time flag to be included in the thread based on a property corresponding to the thread. The scheduler is used for selecting a prior thread to be executed by the specific processor. According to the real-time flag of the prior thread, the adjusting circuit sets the acceptance for the shared peripheral interrupt recorded in the register. When assigning interrupts to the processors, the interrupt controller considers the acceptance recorded in the register.
3
TW201919344A
Signal receiving apparatus and signal processing method thereof
Publication/Patent Number: TW201919344A Publication Date: 2019-05-16 Application Number: 106138847 Filing Date: 2017-11-09 Inventor: Cheng, Kai-wen   Chen, Chia-wei   Lai, Ko-yin   Assignee: MStar Semiconductor, Inc   IPC: H04B1/16 Abstract: A signal receiving apparatus including an oscillating circuit, an interpolation circuit, a matched filter, a high-pass filter, and a timing recovery circuit is provided. The oscillating circuit generates a clock signal. Based on the clock signal, the interpolation circuit performs an interpolation process on an input signal, so as to generate an interpolation result. The matched filter is used for demodulating the interpolation result, so as to generate an output signal. The high-pass filter performs a high-pass process on the interpolation result, so as to generate a filtered signal. The timing recovery circuit receives the filtered signal and performs a timing recovery process according to the filtered signal.
4
TW201929182A
Electrostatic discharge protection apparatus
Publication/Patent Number: TW201929182A Publication Date: 2019-07-16 Application Number: 106146063 Filing Date: 2017-12-27 Inventor: Yeh, Yen-hung   Lai, Po-ya   Federico, Agustin Altolaguirre   Assignee: MStar Semiconductor, Inc   IPC: H01L23/60 Abstract: An electrostatic discharge (ESD) protection apparatus is provided. A first power rail provides a first reference voltage. A second power rail provides a second reference voltage. A detection circuit generates a detection result based on whether an ESD stress occurs on the first power rail. A first N-type MOSFET is coupled between the first power rail and a common node; its gate is a first control terminal. A second N-type MOSFET is coupled between the common node and the second power rail; its gate is a second control terminal. An intermediate power rail provides an intermediate voltage between the first and second reference voltages. According to the detection result, a first switching circuit determines to couple the first control terminal with the first power rail or the intermediate power rail. According to the detection result, a second switching circuit determines to couple the second control terminal with the second power rail or the first control terminal.
5
TW201941584A
Apparatus and method for phase recovery applied in receiving end of DVB-S system
Publication/Patent Number: TW201941584A Publication Date: 2019-10-16 Application Number: 107109596 Filing Date: 2018-03-21 Inventor: Cheng, Kai-wen   Tung, Tai-lai   Cho, Ting-nan   Assignee: MStar Semiconductor, Inc   IPC: H04N5/44 Abstract: A phase recovery apparatus is provided. By compensating N segments of known data and N segments of unknown data based on a phase compensating signal, a phase compensating circuit generates N segments of compensated known data and N segments of compensated unknown data. A phase estimating circuit generates an i th estimated phase based on the i th segment of compensated known data. An initial value setting circuit generates N initial phase errors, wherein the i th initial phase error is related to the i th estimated phase and at least one initial phase error is also related to one or more other estimated phases. According to the i th initial phase error, the phase compensating signal to be applied on the i th segment of unknown data is initialized. By performing a phase tracking process on the i th segment of unknown data, the phase tracking circuit adjusts the phase compensating signal.
6
TW201919348A
Signal receiving apparatus and signal processing method thereof
Publication/Patent Number: TW201919348A Publication Date: 2019-05-16 Application Number: 106139368 Filing Date: 2017-11-14 Inventor: Cheng, Kai-wen   Chen, Chia-wei   Liao, Yi-ying   Tung, Tai-lai   Assignee: MStar Semiconductor, Inc   IPC: H04B1/18 Abstract: A signal receiving apparatus including a scaling circuit, an iterative decoder, and a control circuit is provided. According to a scaling ratio, the scaling circuit changes the scale of an input signal, so as to correspondingly generate a scaled signal. The iterative decoder performs an iterative decoding process on the scaled signal. Based on the total number of iterations that the iterative decoder performed on N data segments in the scaled signal, the control circuit generates an modified scaling ratio for the scaling circuit, wherein N represents a predetermined positive integer.
7
TW201924349A
Image processing apparatus and image processing method related to motion compensation
Publication/Patent Number: TW201924349A Publication Date: 2019-06-16 Application Number: 106139902 Filing Date: 2017-11-17 Inventor: Wang, Tai-chi   Teng, Shu-wei   Assignee: MStar Semiconductor, Inc   IPC: H04N19/513 Abstract: An image processing apparatus including a search range providing circuit, a searching circuit, and an encoder is provided. The search range providing circuit collects N predicted motion vectors for a target image block and accordingly sets N corresponding search ranges located in a reference frame. The symbol N represents an integer larger than one. The searching circuit performs a motion compensation search process in the N search ranges, so as to select a motion vector for the target image block. The encoder encodes the target image block based on the selected motion vector.
8
TW201933122A
Memory controlling device and memory controlling method
Publication/Patent Number: TW201933122A Publication Date: 2019-08-16 Application Number: 107102114 Filing Date: 2018-01-19 Inventor: Huang, Chien-hsing   Assignee: MStar Semiconductor, Inc   IPC: G06F12/10 Abstract: A memory controlling device and a memory controlling method are provided. The memory controlling method includes the following steps: A physical address of a memory is received from a function circuit. A range lookup table is used to determine a range ID according to the physical address. An authority lookup table is used to determine an authority of the function circuit operating at the physical address of the memory according to a device ID and the range ID.
9
TW201916607A
Wireless communication system and signal processing method thereof
Publication/Patent Number: TW201916607A Publication Date: 2019-04-16 Application Number: 106133644 Filing Date: 2017-09-29 Inventor: Kuo, Chih-cheng   Tung, Tai-lai   Assignee: MStar Semiconductor, Inc   IPC: H04B15/00 Abstract: A wireless communication system including a channel estimating circuit, a shortening circuit, a time-domain decision-feedback equalizer, and a coefficient calculating circuit is provided. The channel estimating circuit generates an estimated channel impulse response based on a received signal. According to a main energy distribution region of the estimated channel impulse response, the shortening circuit cuts out a shortened impulse response from the estimated channel impulse response. The time-domain decision-feedback equalizer is used for performing a time-domain equalizing process on the received signal and includes a feedforward filter for filtering the received signal. The coefficient calculating circuit is used for performing calculation based on the shortened impulse response, so as to generate a set of feedforward filtering coefficients utilized by the feedforward filter.
10
TWI646785B
Wireless communication system and signal processing method thereof
Publication/Patent Number: TWI646785B Publication Date: 2019-01-01 Application Number: 106133644 Filing Date: 2017-09-29 Inventor: Kuo, Chih-cheng   Tung, Tai-lai   Assignee: MStar Semiconductor, Inc   IPC: H04B15/00 Abstract: A wireless communication system including a channel estimating circuit, a shortening circuit, a time-domain decision-feedback equalizer, and a coefficient calculating circuit is provided. The channel estimating circuit generates an estimated channel impulse response based on a received signal. According to a main energy distribution region of the estimated channel impulse response, the shortening circuit cuts out a shortened impulse response from the estimated channel impulse response. The time-domain decision-feedback equalizer is used for performing a time-domain equalizing process on the received signal and includes a feedforward filter for filtering the received signal. The coefficient calculating circuit is used for performing calculation based on the shortened impulse response, so as to generate a set of feedforward filtering coefficients utilized by the feedforward filter.
11
TW201941590A
Channel scan apparatus and channel scan method in satellite TV system
Publication/Patent Number: TW201941590A Publication Date: 2019-10-16 Application Number: 107109406 Filing Date: 2018-03-20 Inventor: Liao, Yi-ying   Tung, Tai-lai   Assignee: MStar Semiconductor, Inc   IPC: H04N5/50 Abstract: A channel scan apparatus in a satellite TV system is provided. The channel scan apparatus includes a spectrum generating circuit, a memory, and an artificial neural network. The spectrum generating circuit is used for receiving and performing a spectrum analysis on a TV signal, so as to generate its spectrum. The memory is used for storing a set of parameters previously generated based on plural spectrum samples. The artificial neural network includes plural neuron circuits. With the set of parameters, the artificial neural network performs a neural network computation on the spectrum of the TV signal, so as to generate a channel scan result. The set of parameters includes a bias and one or more weights utilized by each neuron circuit among the plural neuron circuits when performing the neural network computation.
12
TW201919357A
Signal receiving apparatus conforming to Multimedia over Coax Alliance standard and signal processing method thereof
Publication/Patent Number: TW201919357A Publication Date: 2019-05-16 Application Number: 106138261 Filing Date: 2017-11-06 Inventor: Tung, Tai-lai   Tsai, Teng-han   Assignee: MStar Semiconductor, Inc   IPC: H04B17/21 Abstract: A signal receiving apparatus conforming to Multimedia over Coax Alliance (MoCA) standards is provided. The apparatus includes a main estimating circuit, an auxiliary estimating circuit, a combining circuit, and an equalizing circuit. The main estimating circuit generates a main channel impulse response based on plural channel estimation symbols in a received signal. The auxiliary estimating circuit generates an auxiliary channel impulse response based on at least one long symbol in the received signal. The combining circuit generates a combined channel impulse response based on the main and auxiliary channel impulse responses. The equalizing circuit performs a equalization process based on the combined channel impulse response.
13
TW201944770A
Display apparatus and signal processing method thereof
Publication/Patent Number: TW201944770A Publication Date: 2019-11-16 Application Number: 107113720 Filing Date: 2018-04-23 Inventor: Huang, Chin-yi   Hsu, Cheng-che   Lu, Fu-min   Assignee: MStar Semiconductor, Inc   IPC: H04N5/93 Abstract: A display apparatus including a video processor, a graphic processor, a combining circuit, a retrieving circuit, and a graphic controller is provided. The video processor processes a target video data and generates a corresponding video signal. The graphic processor processes a graphic data and generates a corresponding graphic signal. When the target video data is changed from a first video data to a second video data, the retrieving circuit retrieves a static picture related to the first video data from the video processor, so as to generate a retrieved result. The graphic controller sets the retrieved result as the graphic data provided to the graphic processor. The combining circuit combines the the graphic signal related to the retrieved result above the video signal, so as to generate an output video signal.
14
US2019080638A1
CIRCUIT APPLIED TO DISPLAY APPARATUS AND ASSOCIATED SIGNAL PROCESSING METHOD
Publication/Patent Number: US2019080638A1 Publication Date: 2019-03-14 Application Number: 15/968,792 Filing Date: 2018-05-02 Inventor: Yang, Tzu-yi   Lai, Ko-yin   Tung, Tai-lai   Assignee: Mstar semiconductor inc   IPC: G09G3/00 Abstract: A circuit applied to a display apparatus includes an analog-to-digital converter (ADC), a filter and impulsive interference detecting circuit. The ADC converts an analog input signal to a digital input signal. The filter filters out adjacent-channel interference (ACI) of the digital input signal to generate a filtered digital input signal. The impulsive interference detecting circuit detects a noise intensity of a part of a frequency range of the filtered digital input signal to generate a detection result. The part of the frequency range is smaller than a frequency band of the filter, and the detection result is used to determine whether the analog input signal has impulsive interference.
15
US2019052920A1
ROLL-OFF PARAMETER DETERMINING METHOD AND MODULE
Publication/Patent Number: US2019052920A1 Publication Date: 2019-02-14 Application Number: 15/890,643 Filing Date: 2018-02-07 Inventor: Lai, Szu-hsiang   Chou, Yu-shen   Cheng, Kai-wen   Assignee: Mstar semiconductor inc   IPC: H04N21/266 Abstract: A roll-off parameter determining module disposed at a receiving terminal is provided. The receiving terminal receives first roll-off information of a first frame and second roll-off information of a second frame. The first frame is adjacent to the second frame. The module for determining a roll-off parameter includes: a register unit; a first determining unit, determining whether one of the first roll-off information and the second roll-off information includes a first data type, and generating a first roll-off parameter indicator; a second determining unit, determining whether one of the first roll-off information and the second roll-off information includes a second data type and outputting a second roll-off parameter indicator; and a look-up table (LUT) unit, looking up an LUT according to the first roll-off parameter indicator and a second roll-off parameter indicator to output a roll-off parameter.
16
US2019289300A1
IMAGE COMPRESSION SYSTEM AND IMAGE COMPRESSION METHOD USING IMAGE COMPRESSION SYSTEM
Publication/Patent Number: US2019289300A1 Publication Date: 2019-09-19 Application Number: 16/141,185 Filing Date: 2018-09-25 Inventor: Huang, Yi-chin   Tung, Yi-shin   Assignee: Mstar semiconductor inc   IPC: H04N19/172 Abstract: A method for compressing an image frame. Display data of a plurality of image blocks in the image frame is transmitted in a raster san order to a post-processing circuit. Upon receiving the display data of one image block, the post-processing circuit reads intermediate data of a buffering image block corresponding to the image block from a buffer memory, performs post-processing on the intermediate data of the buffering image block and display data of a main sub-block in the image block according to the display data of the image block and the intermediate data of the buffering image block to generate post-processed data of a post-processed image block, and stores the intermediate data of an intermediate image block in the image block to the buffer memory. A compressor compresses the post-processed data of the post-processed image block into compression data of the post-processed image block.
17
US2019355089A1
IMAGE MOTION COMPENSATION DEVICE AND METHOD
Publication/Patent Number: US2019355089A1 Publication Date: 2019-11-21 Application Number: 16/170,713 Filing Date: 2018-10-25 Inventor: Liu, Bang-sian   Tseng, Yu-cheng   Assignee: Mstar semiconductor inc   IPC: G06T1/60 Abstract: An image motion compensation device includes: a motion vector information processing circuit, generating an image interpolation phase and a motion vector status according to motion vector information of a front image and a rear image; a cache memory circuit, allocates first and second memory spaces to respectively store first-range pixels of the front image and second-range pixels of the rear image read from an external memory circuit; a memory allocation control circuit, generating an allocation control signal according to the image interpolation phase and the motion vector status to control the cache memory circuit to dynamically allocate sizes of the first and second memory spaces; and an image motion compensation circuit, generating, based on the first-range and second-range pixels, an interpolation image corresponding to the image interpolation phase according to the motion vector information and the allocation control signal.
18
US2019214075A1
CIRCUIT FOR CONTROLLING MEMORY AND ASSOCIATED METHOD
Publication/Patent Number: US2019214075A1 Publication Date: 2019-07-11 Application Number: 16/056,802 Filing Date: 2018-08-07 Inventor: Chen, Chung-ching   Lin, Chen-nan   Chuang, Che-wei   Assignee: Mstar semiconductor inc   IPC: G11C11/406 Abstract: A circuit for controlling a memory includes a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator generates at least one frequency control signal. The clock generator, coupled to the frequency generator, increases or decreases the frequency of a clock signal by a multiple number of times according to the frequency control signal, such that the frequency of the clock signal is adjusted from an initial frequency to a target frequency. The memory controller, coupled to the clock generator, receives the clock signal and controls the memory according to the clock signal.
19
US2019197665A1
IMAGE STITCHING METHOD AND DEVICE
Publication/Patent Number: US2019197665A1 Publication Date: 2019-06-27 Application Number: 16/056,747 Filing Date: 2018-08-07 Inventor: Huang, Ren-you   Assignee: Mstar semiconductor inc   IPC: G06T3/40 Abstract: A present invention discloses an image stitching method and an image stitching device for stitching a first image and a second image. The image stitching method includes: calculating, according to pixel values of the first image and the second image in an overlapping area, a plurality of costs respectively corresponding to a plurality of positions in the overlapping area; calculating, according to the plurality of costs and relative distances between the plurality of positions, a plurality of forward regularized cumulative costs respectively corresponding to the plurality of positions in the overlapping area; determining a seam in the overlapping area according to the plurality of forward regularized cumulative costs, wherein the seam includes a plurality of stitching positions; and stitching the first image and the second image on the basis of the seam to generate a stitched image.
20
US2019238795A1
METHOD AND SYSTEM ENCRYPTING AND DECRYPTING AUDIO/VIDEO FILE
Publication/Patent Number: US2019238795A1 Publication Date: 2019-08-01 Application Number: 16/188,707 Filing Date: 2018-11-13 Inventor: Chen, Lijing   Assignee: Mstar semiconductor inc   IPC: H04N21/6334 Abstract: An encrypting and decrypting method applied to a system including at least one camera device and a hard disk video decoder includes: transmitting a handshake signal to the camera device which supports an encryption function and has selected the encryption function, wherein the handshake signal includes first identifier information uniquely corresponding to a chip of the hard disk video recorder; receiving the handshake signal; generating a key according to the first identifier information of the hard disk video recorder in the handshake signal and second identifier information uniquely corresponding to a chip of the camera device; encrypting an audio/video file recorded by the camera device according to the key to generate an encrypted audio/video file bitstream; and receiving and decrypting the encrypted audio/video file bitstream.
Total 212 pages