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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2021028103A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021028103A1 Publication Date: 2021-01-28 Application Number: 16/517,998 Filing Date: 2019-07-22 Inventor: Huang, Tse-yao   Shih, Shing-yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/522 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first conductive elements separately positioned above the semiconductor substrate, a plurality of first supporting pillars respectively correspondingly positioned between an adjacent pairs of the plurality of first set conductive elements, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars.
2
US2021074639A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021074639A1 Publication Date: 2021-03-11 Application Number: 16/561,489 Filing Date: 2019-09-05 Inventor: Huang, Tse-yao   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/532 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a first lattice constant, a first word line positioned in the substrate, and a plurality of stress regions positioned adjacent to lower portions of sidewalls of the first word line. The plurality of stress regions have a second lattice constant, the second lattice constant of the plurality of stress regions is different from the first lattice constant of the substrate.
3
US2021091028A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021091028A1 Publication Date: 2021-03-25 Application Number: 16/582,191 Filing Date: 2019-09-25 Inventor: Hsu, Ping   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of conductive features positioned above the substrate, a plurality of landing pads positioned above the substrate, a coverage layer positioned above the substrate, and a plurality of capacitor structures positioned above the substrate. An angle between the axes of two adjacent landing pads is less than 180 degrees.
4
US2021091088A1
SEMICONDUCTOR DEVICE WITH NANOWIRE CAPACITOR PLUGS AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021091088A1 Publication Date: 2021-03-25 Application Number: 16/582,337 Filing Date: 2019-09-25 Inventor: Tsai, Tzu-ching   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L27/108 Abstract: The present application discloses a semiconductor device with nanowire plugs and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having first regions and second regions; a plurality of capacitor contacts positioned over the second regions, at least one of the capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the first regions and a plurality of bit lines positioned over the bit line contacts; a plurality of capacitor plugs disposed over the capacitor contacts, wherein at least one of the plurality of capacitor plugs includes a plurality of nanowires, a conductive liner disposed over the nanowires, and a conductor disposed over the conductive liner; and a plurality of capacitor structures disposed respectively over the capacitor plugs.
5
US2021082843A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021082843A1 Publication Date: 2021-03-18 Application Number: 16/573,549 Filing Date: 2019-09-17 Inventor: Hsu, Ping   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first conductive body, a second conductive body positioned separate from the first conductive body, a plurality of liners respectively correspondingly attached to a side surface of the first conductive body and a side surface of the second conductive body, and a first insulating segment positioned between the first conductive body and the second conductive body.
6
US2021082834A1
INTERCONNECT STRUCTURE
Publication/Patent Number: US2021082834A1 Publication Date: 2021-03-18 Application Number: 17/105,480 Filing Date: 2020-11-25 Inventor: Kang, Ting-cih   Chiu, Hsih-yang   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/552 Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.
7
US10951206B1
Off chip driving system and signal compensation method
Publication/Patent Number: US10951206B1 Publication Date: 2021-03-16 Application Number: 16/986,246 Filing Date: 2020-08-05 Inventor: Wu, Chang-ting   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H03K17/16 Abstract: An off chip driving system includes a decision circuit, multiple first and second adjustable-enhancement circuits, and multiple first and second drivers. The decision circuit outputs a first and a second decision signal according to a clock and an input data. Each first adjustable-enhancement circuit generates one of first control signals in response to the first and the second decision signal and one of first optional signals. Each second adjustable-enhancement circuit generates one of second control signals in response to the first and the second decision signal and one of second optional signals. Each first driver is coupled to the corresponding first adjustable-enhancement circuit and configured to be enabled in response to the corresponding first control signal. Each second driver is coupled to the corresponding second adjustable-enhancement circuit and configured to be enabled in response to the corresponding second control signal.
8
US2021028310A1
SEMICONDUCTOR MEMORY STRUCTURE HAVING DRAIN STRESSOR, SOURCE STRESSOR AND BURIED GATE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2021028310A1 Publication Date: 2021-01-28 Application Number: 16/520,569 Filing Date: 2019-07-24 Inventor: Fan, Cheng-hsiang   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L29/78 Abstract: The present disclosure provides a semiconductor memory structure and a method for preparing the semiconductor memory structure. The semiconductor memory structure includes a substrate, a gate structure, a drain stressor and a source stressor. The gate structure is disposed in the substrate. Each of the source stressor and the drain stressor includes a strained part disposed in the substrate.
9
US2021028054A1
SEMICONDUCTOR DEVICE WITH AIR SPACER AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2021028054A1 Publication Date: 2021-01-28 Application Number: 16/520,656 Filing Date: 2019-07-24 Inventor: Yeh, Huan-yung   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/764 Abstract: The present disclosure provides a semiconductor device and a method for forming the semiconductor device. The method includes forming a first conductive structure over a substrate, forming a first dielectric structure over the first conductive structure, transforming a sidewall portion of the first conductive structure into a first dielectric portion, removing the first dielectric portion such that a width of the first dielectric structure is greater than a width of a remaining portion of the first conductive structure, and forming an inter-layer dielectric (ILD) layer covering sidewalls of the first dielectric structure such that a first air spacer is formed between the ILD layer and the remaining portion of the first conductive structure.
10
US2021050232A1
WAFER CLEANING APPARATUS AND OPERATION METHOD OF THE SAME
Publication/Patent Number: US2021050232A1 Publication Date: 2021-02-18 Application Number: 16/537,638 Filing Date: 2019-08-12 Inventor: Doong, Shyue-ru   Tsai, Feng-ju   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/67 Abstract: A wafer cleaning apparatus includes a spin base, a first arm, and a second arm. The spin base is configured to support a wafer. The first arm is disposed above the spin base and configured to supply a chemical solution. The second arm is movably positioned above the spin base, and the second arm is configured to supply a first cleaning solution above the spin base when the first arm abnormally stops supplying the chemical solution.
11
US10910357B2
Semiconductor package including hybrid bonding structure and method for preparing the same
Publication/Patent Number: US10910357B2 Publication Date: 2021-02-02 Application Number: 16/360,619 Filing Date: 2019-03-21 Inventor: Shih, Shing-yih   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L25/18 Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a first die, a second die and a hybrid bonding structure disposed between the first die and the second die. The first die includes a first front side and a first back side opposite to the first front side. The second die includes a second front side and a second back side opposite to the second front side. The hybrid bonding structure is disposed between the first back side of the first die and the second front side of the second die. The first die and the second die are bonded to each other by the hybrid bonding structure. The hybrid bonding structure includes an organic barrier layer and an inorganic barrier layer bonded to each other.
12
US2021098464A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021098464A1 Publication Date: 2021-04-01 Application Number: 16/585,598 Filing Date: 2019-09-27 Inventor: Huang, Tse-yao   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L27/108 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric structure disposed over the substrate; a bit line bottom contact disposed in the dielectric structure; a composite decoupling structure disposed between the dielectric structure and the bit line bottom contact, wherein the composite decoupling structure comprises an air gap and a dielectric spacer; a bit line top contact disposed over the bit line bottom contact; and a bit line to disposed over the bit line top contact.
13
US2021098447A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2021098447A1 Publication Date: 2021-04-01 Application Number: 16/585,461 Filing Date: 2019-09-27 Inventor: Huang, Tse-yao   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L27/06 Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a gate structure comprising a gate bottom insulating layer inwardly positioned, a gate top insulating layer positioned on the gate bottom insulating layer, a gate top conductive layer positioned on the gate top insulating layer, and a gate filler layer positioned on the gate top conductive layer; and a capacitor structure comprising a capacitor bottom insulating layer inwardly positioned, a capacitor bottom conductive layer positioned on the capacitor bottom insulating layer, a capacitor top insulating layer positioned on the capacitor bottom conductive layer, a capacitor top conductive layer positioned on the capacitor top insulating layer, and a capacitor filler layer positioned on the capacitor top conductive layer. The gate bottom insulating layer is formed of a same material as the capacitor bottom insulating layer.
14
US2021020762A1
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME
Publication/Patent Number: US2021020762A1 Publication Date: 2021-01-21 Application Number: 16/511,602 Filing Date: 2019-07-15 Inventor: Lin, Yuan-yuan   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L29/66 Abstract: The present application discloses a semiconductor device structure and a method for preparing the same. The method includes forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.
15
US10903103B2
Front opening unified pod
Publication/Patent Number: US10903103B2 Publication Date: 2021-01-26 Application Number: 15/876,214 Filing Date: 2018-01-22 Inventor: Kuan, Shih-fan   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/673 Abstract: A front opening unified pod (FOUP) includes a container, a plurality of wafer slots, at least one inlet pipe, and at least one outlet pipe. The wafer slots, the inlet pipe, and the outlet pipe are disposed in the container. The inlet pipe has a plurality of exhale openings arranged along the inlet pipe. The outlet pipe has a plurality of inhale openings arranged along the outlet pipe.
16
US10937754B1
Semiconductor package and manufacturing method thereof
Publication/Patent Number: US10937754B1 Publication Date: 2021-03-02 Application Number: 16/594,059 Filing Date: 2019-10-06 Inventor: Yang, Wu-der   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/31 Abstract: A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a number of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member is configured for coupling the first die and the second die and comprises a first connection plate, a second connection plate and a bump. The first connection plate is connected to the first die. The second connection plate is connected to the second die. The bump couples the first connection plate and the second connection plate. The bonding wires couple the interconnection member to the package substrate, the first die and the second die.
17
US10937790B1
Semiconductor device with air gap structure and method for preparing the same
Publication/Patent Number: US10937790B1 Publication Date: 2021-03-02 Application Number: 16/540,493 Filing Date: 2019-08-14 Inventor: Su, Kuo-hui   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L27/108 Abstract: A semiconductor device includes a first bit line disposed over a semiconductor substrate. The semiconductor device also includes a capacitor contact and a dielectric structure disposed over the semiconductor substrate and adjacent to the first bit line. The capacitor contact, the dielectric structure and the first bit line are separated from one another by an air gap structure.
18
US2021090939A1
SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2021090939A1 Publication Date: 2021-03-25 Application Number: 16/578,814 Filing Date: 2019-09-23 Inventor: Huang, Tse-yao   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: A semiconductor device structure includes a first conductive structure and a second conductive structure disposed over a semiconductor substrate. The semiconductor device structure also includes a first spacer disposed over the first conductive structure, and a second spacer disposed over the second conductive structure. The semiconductor device structure further includes a third spacer disposed over a sidewall of the first spacer, and a fourth spacer disposed over a sidewall of the second spacer. A lower portion of the third spacer adjoins a lower portion of the fourth spacer, and an air gap is covered by the lower portion of the third spacer and the lower portion of the fourth spacer.