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1 | US2021005652A1 |
IMAGE SENSING DEVICE
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Publication/Patent Number: US2021005652A1 | Publication Date: 2021-01-07 | Application Number: 16/597,572 | Filing Date: 2019-10-09 | Inventor： Gu, Tae Lim Yang, Yun Hui | Assignee: Sk hynix inc | IPC: H01L27/146 | Abstract: An image sensing device includes a photoelectric conversion element configured to generate photocharges in response to incident light, a floating diffusion configured to temporarily store the photocharges generated by the photoelectric conversion element, and a transfer gate configured to transmit the photocharges generated by the photoelectric conversion element to the floating diffusion region. The transfer gate includes a main transfer gate disposed to overlap a center section of the photoelectric conversion element and configured to operate in response to a first transmission signal, and a sub transfer gate disposed to overlap a boundary region of the photoelectric conversion element and configured to operate in response to a second potential level different from the first potential level. | |||
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2 | US10884961B2 |
Dynamic termination circuit, semiconductor apparatus and system including the same
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Publication/Patent Number: US10884961B2 | Publication Date: 2021-01-05 | Application Number: 15/642,639 | Filing Date: 2017-07-06 | Inventor： Jung, Hae Kang | Assignee: Sk hynix inc | IPC: G06F13/36 | Abstract: A semiconductor apparatus may include a receiver circuit and a termination circuit. The receiver circuit may be coupled to a receiving node, and configured to receive a signal transmitted through a signal transmission line. The termination circuit may be configured to be turned on to set a resistance value of the receiving node in a transition period of the signal, and turned off in a stabilization period of the signal. | |||
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3 | US2021004324A1 |
MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD
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Publication/Patent Number: US2021004324A1 | Publication Date: 2021-01-07 | Application Number: 16/774,287 | Filing Date: 2020-01-28 | Inventor： Kang, Hye Mi Byun, Eu Joon | Assignee: Sk hynix inc | IPC: G06F12/02 | Abstract: A memory system, a memory controller and an operating method are disclosed. By determining a time for garbage collection, based on information for a write command group including a plurality of write commands inputted from a host, it is possible to minimize a time in which processing a command transmitted from the host is delayed due to garbage collection, and ensure stable write performance. | |||
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4 | US2021005527A1 |
STACKED SEMICONDUCTOR PACKAGE HAVING HEAT DISSIPATION STRUCTURE
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Publication/Patent Number: US2021005527A1 | Publication Date: 2021-01-07 | Application Number: 16/668,979 | Filing Date: 2019-10-30 | Inventor： Choi, Bok Kyu Kim, Jong Hoon Kim, Ki Bum | Assignee: Sk hynix inc | IPC: H01L23/367 | Abstract: A stacked semiconductor package includes a first die, a second die stacked on a surface of the first die, a heat dissipation layer disposed on the surface, a heat insulation layer disposed on the surface to cover the heat dissipation layer and the first die, a heat sink disposed on the second die, and a heat conduction structure spaced apart from the second die in a lateral direction on the surface to connect the heat dissipation layer to the heat sink. | |||
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5 | US10884947B2 |
Methods and memory systems for address mapping
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Publication/Patent Number: US10884947B2 | Publication Date: 2021-01-05 | Application Number: 16/194,117 | Filing Date: 2018-11-16 | Inventor： Bhatia, Aman Zhang, Fan Kumar, Naveen Cai, Yu | Assignee: Sk hynix inc | IPC: G06F12/00 | Abstract: Methods and systems are provided for an address mapping scheme using a hash table. A controller of a memory system partitions a plurality of physical blocks included in a memory device into a plurality of data blocks and a plurality of log blocks, translates a logical address to a physical address based on a block-level mapping scheme or a page-level mapping scheme using a hash table, and performs a read and/or write operation based on the translated physical address. | |||
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6 | US10885623B2 |
Methods of detecting joint failures between stacked semiconductor dies
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Publication/Patent Number: US10885623B2 | Publication Date: 2021-01-05 | Application Number: 16/186,261 | Filing Date: 2018-11-09 | Inventor： Jung, Hae Won | Assignee: Sk hynix inc | IPC: G06K9/00 | Abstract: A method of detecting a joint failure of a semiconductor die stack is provided. The method may include providing the semiconductor die stack including a base substrate, a lower semiconductor die stacked on the base substrate, and an upper semiconductor die stacked on the lower semiconductor die opposite to the base substrate. The lower semiconductor die may include first through silicon vias (TSVs). Heat may be supplied to a bottom surface of the base substrate opposite to the lower semiconductor die. A thermographic image of a top surface of the upper semiconductor die opposite to the lower semiconductor die may be obtained. Whether the joint failure exists in the semiconductor die stack may be discriminated, with the thermographic image, based on a temperature difference between regions of the thermographic image corresponding with regions of the first TSVs. | |||
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7 | US10885958B2 |
Semiconductor device with phase difference detection circuit between a clock and strobe signal
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Publication/Patent Number: US10885958B2 | Publication Date: 2021-01-05 | Application Number: 16/192,479 | Filing Date: 2018-11-15 | Inventor： Lim, Yu Ri Yoon, Sangsic | Assignee: Sk hynix inc | IPC: G11C7/22 | Abstract: A semiconductor device includes a phase difference detection circuit configured to generate a detection signal by detecting a phase difference of a clock and a strobe signal, the detection signal being generated at a logic level of the strobe signal in synchronization with the clock, and configured to generate a write clock by delaying the strobe signal. The semiconductor device also includes a control signal generation circuit configured to store the detection signal, in synchronization with the write clock, and configured to output the stored detection signal as a control signal. | |||
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8 | US10885989B1 |
Data storage apparatus and internal voltage trimming circuit and method for trimming an internal voltage
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Publication/Patent Number: US10885989B1 | Publication Date: 2021-01-05 | Application Number: 16/806,644 | Filing Date: 2020-03-02 | Inventor： Moon, Young Jin | Assignee: Sk hynix inc | IPC: G11C16/30 | Abstract: A data storage apparatus includes storage and a controller configured to control the storage in response to a request from a host. The controller includes an internal voltage trimming circuit which includes: an integration circuit configured to generate an integration signal by integrating a difference between a test voltage output from a device under test (DUT) and a reference voltage; a comparison circuit configured to generate a comparison signal by comparing the integration signal and the reference voltage; a transition detection circuit configured to output a detection signal according to level transition of the comparison signal; a counter configured to receive an initial trimming code and generate a preliminary trimming code by increasing or reducing the initial trimming code in response to the detection signal; and an average circuit configured to generate a final trimming code by averaging the preliminary trimming code for a determined time interval and provide the final trimming code to the storage. | |||
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9 | US10885992B2 |
Memory system and operating method thereof
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Publication/Patent Number: US10885992B2 | Publication Date: 2021-01-05 | Application Number: 16/597,251 | Filing Date: 2019-10-09 | Inventor： Lee, Joo-young | Assignee: Sk hynix inc | IPC: G11C16/04 | Abstract: A memory system includes: a memory device; a run-time bad block detector suitable for storing information of super memory blocks, each including a run-time bad block, in a bad list; a bit-map manager suitable for generating a bit-map representing integrity information of memory blocks in each of the super memory blocks; a short super block manager suitable for designating, among the super memory blocks, a super memory block having a number of run-time bad blocks less than or equal to a threshold as a short super memory block based on the bad list and the bit-map, whenever a logical unit configuration command is received from a host; and a processor suitable for controlling the memory device to simultaneously access normal blocks among the memory blocks forming the designated short super memory block and to perform a normal operation, based on the bit-map. | |||
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10 | US10886003B2 |
Semiconductor memory device, operating method thereof, and memory system
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Publication/Patent Number: US10886003B2 | Publication Date: 2021-01-05 | Application Number: 16/262,347 | Filing Date: 2019-01-30 | Inventor： Lee, Jae Ho | Assignee: Sk hynix inc | IPC: G11C16/32 | Abstract: A semiconductor memory device includes a switching controller, a voltage generator and control logic. The switching controller is connected to a local word line. The voltage generator, connected to the switching controller, is configured to generate an operating voltage according to an input clock signal and transfer the operating voltage to the switching controller. The control logic is configured to control operations of the voltage generator and the switching controller. The control logic is configured to detect an amount of leakage current of the local word line by counting a number of pulses of the input clock signal. | |||
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11 | US2021005233A1 |
MEMORY DEVICE AND METHOD OF OPERATING THE SAME
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Publication/Patent Number: US2021005233A1 | Publication Date: 2021-01-07 | Application Number: 16/773,643 | Filing Date: 2020-01-27 | Inventor： Kim, Heon Ki Ok, Sung Hwa | Assignee: Sk hynix inc | IPC: G11C7/22 | Abstract: The present technology relates to a memory device that generates various signals used in a read training operation and a method of operating the memory device. The memory device according to an embodiment of the present disclosure includes an address counter configured to generate a plurality of count signals based on a read training enable signal and a first clock signal received from a memory controller, and an address section identification signal generator configured to generate address section identification signals used in identifying a plurality of address sections based on at least one of the plurality of count signals. | |||
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12 | US2021004180A1 |
MEMORY SYSTEM AND OPERATING METHOD THEREOF
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Publication/Patent Number: US2021004180A1 | Publication Date: 2021-01-07 | Application Number: 16/802,771 | Filing Date: 2020-02-27 | Inventor： Lee, Joo-young Jung, Hoe-seung | Assignee: Sk hynix inc | IPC: G06F3/06 | Abstract: A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue. | |||
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13 | US2021004325A1 |
DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
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Publication/Patent Number: US2021004325A1 | Publication Date: 2021-01-07 | Application Number: 16/658,386 | Filing Date: 2019-10-21 | Inventor： Cho, Dae Gon | Assignee: Sk hynix inc | IPC: G06F12/02 | Abstract: A data storage device may include a memory device including a plurality of memory blocks having a plurality of free memory blocks and a controller configured to control an operation of the memory device, wherein the controller performs a block allocation operation of allocating one or more free memory blocks among the plurality of free memory blocks as one or more programmable memory blocks, and performs a garbage collection (GC) error defense operation of checking whether a GC operation for the plurality of memory blocks has performed successfully, in response to the block allocation operation. | |||
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14 | US2021005267A1 |
MEMORY CONTROLLER, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY SYSTEM
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Publication/Patent Number: US2021005267A1 | Publication Date: 2021-01-07 | Application Number: 17/022,191 | Filing Date: 2020-09-16 | Inventor： Kim, Min Kee | Assignee: Sk hynix inc | IPC: G11C16/26 | Abstract: Provided herein may be a memory controller, a memory system, and a method of operating the memory system. The memory controller may control the operation of a memory device. The memory controller may include a read request buffer, a command generator, and a read request monitor. The read request buffer may be configured to receive a read request from a host. The command generator may be configured to receive the read request from the read request buffer and generate a read command based on the received read request. The read request monitor may be configured to receive read request information about the read request from the read request buffer and determine, based on a stream ID of the read request, whether the read request is a sequential read request. | |||
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15 | US2021005653A1 |
PIXEL AND IMAGE SENSOR INCLUDING THE SAME
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Publication/Patent Number: US2021005653A1 | Publication Date: 2021-01-07 | Application Number: 16/598,917 | Filing Date: 2019-10-10 | Inventor： Jang, Jae Hyung | Assignee: Sk hynix inc | IPC: H01L27/146 | Abstract: A pixel of an image sensor is provided to include a control region and a detection region. The control region is configured to generate hole current in a substrate, and a detection region is configured to capture electrons generated by incident light and moved by the hole current. A depth of an outer detection region of the detection region is deeper than a depth of an inner detection region of the detection region. | |||
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16 | US10885993B2 |
Semiconductor memory device and operating method thereof
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Publication/Patent Number: US10885993B2 | Publication Date: 2021-01-05 | Application Number: 16/598,922 | Filing Date: 2019-10-10 | Inventor： Lee, Hee Youl | Assignee: Sk hynix inc | IPC: G11C16/06 | Abstract: A method of operating a semiconductor memory device includes dummy-programming selected memory cells representing all the memory cells to be programmed for a programming operation. The method also includes determining as a first group of memory cells those selected memory cells having threshold voltages less than or equal to a reference threshold voltage and determining as a second group of memory cells those selected memory cells having threshold voltages greater than the reference threshold voltage. The method further includes programming the selected memory cells by applying a first bit line voltage to the memory cells of the first group, applying a second bit line voltage different from the first bit line voltage to the memory cells of the second group, and applying a same program pulse to the memory cells of the first and second groups. | |||
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17 | US10885995B2 |
Memory controller, memory system including memory controller, method of operating memory controller
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Publication/Patent Number: US10885995B2 | Publication Date: 2021-01-05 | Application Number: 16/513,298 | Filing Date: 2019-07-16 | Inventor： Jung, Sang Hune | Assignee: Sk hynix inc | IPC: G11C16/34 | Abstract: A memory controller for use in a memory system may include a counter configured to count a number of times a read operation corresponding to a read request received from a host is performed; a token manager configured to generate a token each time a count value of the counter reaches a preset count, the token representing a right to perform a background operation; and a operation performing unit configured to perform foreground operations corresponding to the respective requests in response to the requests received from the host, request the token manager to allocate the token to the operation performing unit each time the background operation is triggered, and perform the background operation when the token is allocated from the token manager to the operation performing unit. | |||
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18 | US2021004330A1 |
MEMORY SYSTEM, MEMORY CONTROLLER AND METHOD FOR OPERATING MEMORY SYSTEM
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Publication/Patent Number: US2021004330A1 | Publication Date: 2021-01-07 | Application Number: 16/721,716 | Filing Date: 2019-12-19 | Inventor： Kim, Byung Jun | Assignee: Sk hynix inc | IPC: G06F12/0873 | Abstract: A memory controller, a memory system including the memory controller and a method for operating the memory system are disclosed. The memory controller updates a reference parameter for a memory area in which at least part of the mapping information is stored and determines whether to activate the memory area based on the reference parameter to effectively execute commands received from a host. | |||
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19 | US2021004323A1 |
CONTROLLER, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF
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Publication/Patent Number: US2021004323A1 | Publication Date: 2021-01-07 | Application Number: 16/690,643 | Filing Date: 2019-11-21 | Inventor： Kang, Hye Mi | Assignee: Sk hynix inc | IPC: G06F12/02 | Abstract: There are provided a controller, a memory system having the same, and an operating method thereof. The controller includes a read counter configured to store a block read count value of a super block and memory blocks within a non-super block as a status information in an internal memory by counting a number of times that a read operation is performed on the memory blocks; and a super block manager configured to: store a super block reclaim trigger reference and a non-super block reclaim trigger reference, which is set for the super block and the non-super block, as the status information in the internal memory, divide data stored in the memory blocks into hot data and cold data according to the block read count value, and copy the hot data in the non-super block to the super block according to the status information. | |||
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20 | US2021005260A1 |
SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
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Publication/Patent Number: US2021005260A1 | Publication Date: 2021-01-07 | Application Number: 17/026,402 | Filing Date: 2020-09-21 | Inventor： Joo, Han Soo Park, Bong Yeol Seo, Ji Hyun Lee, Hee Youl | Assignee: Sk hynix inc | IPC: G11C16/04 | Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode. |
3.Current Quota