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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US2020168646A1
INTEGRATED IMAGING DEVICE WITH AN IMPROVED CHARGE STORAGE CAPACITY
Publication/Patent Number: US2020168646A1 Publication Date: 2020-05-28 Application Number: 16/681,161 Filing Date: 2019-11-12 Inventor: Suler, Andrej   Roy, Francois   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L27/146 Abstract: An integrated imaging device includes a pixel having a trench that extends into the substrate. The trench is coated with an insulator and filled with a stack including a first polysilicon region and a second polysilicon region. The first and second polysilicon regions are separated from each other by a layer of insulating material. The first polysilicon region may form a gate electrode of a vertical transistor and the second polysilicon region may form an electrode of a capacitor. An integrated imaging device includes a pixel having a trench that extends into the substrate. The trench is coated with an insulator and filled with a stack including a first polysilicon region and a second polysilicon region. The first and second polysilicon regions are ...More Less
2 US2020233032A1
DETERMINATION OF THE DISPERSION OF AN ELECTRONIC COMPONENT
Publication/Patent Number: US2020233032A1 Publication Date: 2020-07-23 Application Number: 16/745,813 Filing Date: 2020-01-17 Inventor: Carminati, Yann   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G01R31/319 Abstract: A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components configured to conduct a signal. A test device is configured to obtain values of the component test structure and to perform operations on these values. A value representative of a dispersion of a propagation delay of assemblies of electronic components is determined. A component test structure includes stages of components and a logic circuit connected in a ring. Each stage includes two assemblies of similar components ...More Less
3 US10677684B2
Opto electrical test measurement system for integrated photonic devices and circuits
Publication/Patent Number: US10677684B2 Publication Date: 2020-06-09 Application Number: 16/211,511 Filing Date: 2018-12-06 Inventor: Grosse, Philippe   Le, Maitre Patrick   Carpentier, Jean-francois   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G01M11/02 Abstract: An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data. An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing ...More Less
4 US10684326B2
Method and device for testing a chain of flip-flops
Publication/Patent Number: US10684326B2 Publication Date: 2020-06-16 Application Number: 16/031,395 Filing Date: 2018-07-10 Inventor: Clerc, Sylvain   Gasiot, Gilles   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G01R31/3177 Abstract: A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of the clock signal to output a test signal. A comparison is carried out at the cadence of the clock signal of the test signal and the reference signal, where the reference signal is delayed by a delay time taking into account the number of flip-flops in the chain and the length of the test pattern. An output signal is produced, at the cadence of the clock signal, as a result of the comparison. A chain of flip-flops is tested by passing a reference signal through the chain. The reference signal is generated from a test pattern that is cyclically fed back at the cadence of a clock signal. The reference signal propagates through the chain of flip-flops at the cadence of ...More Less
5 US10705294B2
Waveguide termination device
Publication/Patent Number: US10705294B2 Publication Date: 2020-07-07 Application Number: 16/295,553 Filing Date: 2019-03-07 Inventor: Guerber, Sylvain   Baudot, Charles   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G02B6/24 Abstract: An optical waveguide termination device includes a waveguide and metal vias surrounding an end portion of the waveguide. The end portion of the waveguide has a transverse cross-sectional area that decreases towards its distal end. The metal vias are orthogonal to a same plane, with the same plane being orthogonal to the transverse cross-section. The metal vias absorb light originating from the end portion when a light signal propagates through the waveguide, and the metal vias and the end portion provide that an effective index of an optical mode to be propagated through the waveguide progressively varies in the end portion. Additional metal vias may be present along the waveguide upstream of the end portion, with the additional metal vias bordering the waveguide upstream of the end portion providing that the effective index of an optical mode to be propagated through the waveguide varies progressively toward the end portion. An optical waveguide termination device includes a waveguide and metal vias surrounding an end portion of the waveguide. The end portion of the waveguide has a transverse cross-sectional area that decreases towards its distal end. The metal vias are orthogonal to a same plane ...More Less
6 US10535693B2
Infra-red response enhancement for image sensor
Publication/Patent Number: US10535693B2 Publication Date: 2020-01-14 Application Number: 15/916,912 Filing Date: 2018-03-09 Inventor: Roy, Francois   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L27/146 Abstract: A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level. An insulated vertical gate structure separates the region from the well. Buried iInsulated electrodes extend from the front side surface completely through the well and into a portion of the semiconductor body underneath the well. A conductive material portion of each buried insulated electrode is configured to receive a bias voltage and a conductive material portion of insulated vertical gate structure is configured to receive a gate voltage. The semiconductor body is delimited by a capacitive deep trench isolation that is biased at the same voltage as the buried insulated electrode. A semiconductor body of a first conductivity type and doped with a first doping level includes, at a front side surface thereof, a well of a second conductivity type and a region doped with the first conductivity type at a second doping level greater than the first doping level ...More Less
7 US2020068148A1
Integrated Global Shutter Image Sensor
Publication/Patent Number: US2020068148A1 Publication Date: 2020-02-27 Application Number: 16/547,369 Filing Date: 2019-08-21 Inventor: Malinge, Pierre   Lalanne, Frédéric   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H04N5/355 Abstract: In one embodiment, an integrated image sensor includes an array of pixels in which each pixel includes a photosensitive area configured to integrate a luminous signal by generating electron-hole pairs so as to form a first signal representative of the number of electrons in the generated electron-hole pairs and a second signal representative of the number of holes in the generated electron-hole pairs. A first circuit portion is configured to store the first signal sheltered from light. A second circuit portion is configured to store the second signal sheltered from light. A third circuit portion is configured to read the first signal and the second signal and able to perform combination operations between the first signal and the second signal so as to generate a combined signal representative of an image, where the integrated image sensor is tailored to operate in a global shutter control mode. In one embodiment, an integrated image sensor includes an array of pixels in which each pixel includes a photosensitive area configured to integrate a luminous signal by generating electron-hole pairs so as to form a first signal representative of the number of electrons in the ...More Less
8 US10622460B2
Vertical quantum transistor
Publication/Patent Number: US10622460B2 Publication Date: 2020-04-14 Application Number: 16/407,383 Filing Date: 2019-05-09 Inventor: Gauthier, Alexis   Ribes, Guillaume C.   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L29/739 Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region. A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor ...More Less
9 US10656331B2
Integrated photonic device with improved optical coupling
Publication/Patent Number: US10656331B2 Publication Date: 2020-05-19 Application Number: 16/156,601 Filing Date: 2018-10-10 Inventor: Boeuf, Frederic   Baudot, Charles   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G02B6/12 Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal. A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region ...More Less
10 US10658578B2
Memory cell comprising a phase-change material
Publication/Patent Number: US10658578B2 Publication Date: 2020-05-19 Application Number: 16/168,369 Filing Date: 2018-10-23 Inventor: Morin, Pierre   Dutartre, Didier   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L45/00 Abstract: A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10−5 Ω·m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier. A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5·10−5 ...More Less
11 US2020081476A1
BODY BIASING FOR ULTRA-LOW VOLTAGE DIGITAL CIRCUITS
Publication/Patent Number: US2020081476A1 Publication Date: 2020-03-12 Application Number: 16/127,771 Filing Date: 2018-09-11 Inventor: Lallement, Guenole   Abouzeid, Fady   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G05F3/20 Abstract: A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage to the p-body bias nodes of the n-channel MOSFETs. The body bias generator circuit operates in: a first mode to apply a ground supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply a positive supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage; and a second mode to apply the positive supply voltage to the n-body bias nodes of the logic gates as the n-body bias voltage and apply the ground supply voltage to the p-body bias nodes of the logic gates as the p-body bias voltage. A digital circuit includes logic circuitry formed by logic gates. Each logic gate includes a p-channel MOSFET and an n-channel MOSFET. A body bias generator circuit applies an n-body bias voltage to the n-body bias nodes of the p-channel MOSFETs and applies a p-body bias voltage ...More Less
12 US10559611B2
Image sensor
Publication/Patent Number: US10559611B2 Publication Date: 2020-02-11 Application Number: 16/031,710 Filing Date: 2018-07-10 Inventor: Roy, Francois   Are, Philippe   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L27/146 Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer. An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other ...More Less
13 US10684251B2
Ion sensitive field effect transistor (ISFET) having higher sensitivity in response to dynamic biasing
Publication/Patent Number: US10684251B2 Publication Date: 2020-06-16 Application Number: 15/631,078 Filing Date: 2017-06-23 Inventor: Ayele, Getenet Tesega   Monfray, Stephane   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G01N27/414 Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity. A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage ...More Less
14 US2020203547A1
SINGLE-PHOTON AVALANCHE PHOTODIODE
Publication/Patent Number: US2020203547A1 Publication Date: 2020-06-25 Application Number: 16/703,689 Filing Date: 2019-12-04 Inventor: Benhammou, Younes   Golanski, Dominique   Rideau, Denis   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L31/107 Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases. The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the ...More Less
15 US2020150292A1
IONIZING RADIATION DETECTOR
Publication/Patent Number: US2020150292A1 Publication Date: 2020-05-14 Application Number: 16/677,005 Filing Date: 2019-11-07 Inventor: Gasiot, Gilles   Abouzeid, Fady   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: G01T1/24 Abstract: A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a current through the PN junction which changes by a voltage generated across the transistor. This change in voltage is compared to a threshold to detect the ionizing radiation. A diode and a transistor are connected in parallel. The transistor is located on a first doped region forming a PN junction of the diode with a second doped region located under the first region. The circuit functions as an ionizing radiation detection cell by generating a ...More Less
16 US2020043737A1
METHOD FOR SILICIDATION OF SEMICONDUCTOR DEVICE, AND CORRESPONDING SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020043737A1 Publication Date: 2020-02-06 Application Number: 16/515,805 Filing Date: 2019-07-18 Inventor: Monnier, Denis   Gonnard, Olivier   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L21/28 Abstract: A method of fabricating a semiconductor device includes forming a protective layer on a portion of the semiconductor body that is not to be silicided. The protective layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. At least a portion of the silicon nitride layer of the protective layer is removed. A silicided portion of the semiconductor body is laterally spaced from the protective layer. The siliciding is performed by an ion sputtering in a plasma environment on both the silicided portion of the semiconductor body and the portion of the semiconductor body that is not to be silicided. A method of fabricating a semiconductor device includes forming a protective layer on a portion of the semiconductor body that is not to be silicided. The protective layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. At least a portion ...More Less
17 US2020185562A1
SINGLE PHOTON AVALANCHE GATE SENSOR DEVICE
Publication/Patent Number: US2020185562A1 Publication Date: 2020-06-11 Application Number: 16/789,045 Filing Date: 2020-02-12 Inventor: Roy, Francois   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L31/113 Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions. A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region ...More Less
18 US2020211835A1
ETCHING METHOD
Publication/Patent Number: US2020211835A1 Publication Date: 2020-07-02 Application Number: 16/709,251 Filing Date: 2019-12-10 Inventor: Ristoiu, Delia   Bar, Pierre   Leverd, Francois   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L21/02 Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion. The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective ...More Less
19 US2020203211A1
MANUFACTURING OF CAVITIES
Publication/Patent Number: US2020203211A1 Publication Date: 2020-06-25 Application Number: 16/707,614 Filing Date: 2019-12-09 Inventor: Gouraud, Pascal   Ristoiu, Delia   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L21/762 Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion. A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper ...More Less
20 US2020227451A1
BACK-SIDE ILLUMINATED IMAGE SENSOR
Publication/Patent Number: US2020227451A1 Publication Date: 2020-07-16 Application Number: 16/740,050 Filing Date: 2020-01-10 Inventor: Gay, Laurent   Lalanne, Frederic   Henrion, Yann   Guyader, Francois   Fonteneau, Pascal   Seignard, Aurelien   Assignee: STMicroelectronics (Crolles 2) SAS   IPC: H01L27/146 Abstract: Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The capacitive insulation wall includes first and second insulating walls separated by a region of a conductor or a semiconductor material. Portions of the semiconductor layer and the region of the conductor or semiconductor material are selectively etched, and the first and second insulating walls have portions protruding outwardly beyond a back side of the semiconductor layer and of the region of the conductor or semiconductor material. A dielectric passivation layer is deposited on the back side of the structure, and portions of the dielectric passivation layer are locally removed on a back side of the protruding portions of the first and second insulating walls. Image sensors and methods of manufacturing image sensors are provided. One such method includes forming a structure that includes a semiconductor layer extending from a front side to a back side, and a capacitive insulation wall extending through the semiconductor layer. The ...More Less