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1 | EP3528288B1 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3528288B1 | Publication Date: 2020-08-26 | Application Number: 18214935.1 | Filing Date: 2014-06-20 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L27/146 | ||||
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2 | EP3608944A1 |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: EP3608944A1 | Publication Date: 2020-02-12 | Application Number: 19188206.7 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L21/20 | Abstract: A method for removing nuclei formed during a selective epitaxial growth process includes epitaxially growing a first group of one or more semiconductor structures over a substrate with one or more mask layers. A second group of a plurality of semiconductor structures is formed on the one or more mask layers. The method also includes forming one or more protective layers over the first group of one or more semiconductor structures. At least a subset of the second group of the plurality of semiconductor structures is exposed from the one or more protective layers. The method further includes, subsequent to forming the one or more protective layers over the first group of one or more semiconductor structures, etching at least the subset of the second group of the plurality of semiconductor structures. | |||
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3 | US10600640B2 |
Reduction of surface roughness in epitaxially grown germanium by controlled thermal oxidation
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Publication/Patent Number: US10600640B2 | Publication Date: 2020-03-24 | Application Number: 15/624,603 | Filing Date: 2017-06-15 | Inventor： Jung, Woo-shik Na, Yeul Kim, Youngsik Lee, Jae Hyung Lee, Jin Hyung | Assignee: Stratio inc | IPC: H01L21/02 | Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing. | |||
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4 | EP3528288A1 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3528288A1 | Publication Date: 2019-08-21 | Application Number: 18214935.1 | Filing Date: 2014-06-20 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L27/146 | Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | |||
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5 | US2019221595A1 |
Gate-controlled Charge Modulated Device for CMOS Image Sensors
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Publication/Patent Number: US2019221595A1 | Publication Date: 2019-07-18 | Application Number: 16/167,241 | Filing Date: 2018-10-22 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L27/146 | Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | |||
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6 | JP2018129536A |
GATE CONTROL TYPE CHARGING MODULATION DEVICE FOR CMOS IMAGE SENSOR
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Publication/Patent Number: JP2018129536A | Publication Date: 2018-08-16 | Application Number: 2018078326 | Filing Date: 2018-04-16 | Inventor： Lee, Jae-hyung Kim, Youngsik Jung, Woo Shik Na, Yeul | Assignee: STRATIO INC | IPC: H01L31/10 | Abstract: PROBLEM TO BE SOLVED: To provide an optical sensor having a small dark current, a high quantum efficiency, and an enhancement channel modulation.SOLUTION: A device 100 for detecting a light, includes: a first semiconductor region 104 doped by using a first type dopant; and a second semiconductor region 106 doped by using a second type dopant. The second semiconductor region is arranged on an upper direction of the first semiconductor region. The device includes: a gate insulation layer 110; a gate 112; a source 114; and a drain 116. The second semiconductor region includes an upper surface arranged so as to be directed to the gate insulation layer, and a bottom surface arranged on the side opposite to the upper surface of the second semiconductor region. The second semiconductor region includes: an upper part including the upper surface of the second semiconductor region; and a lower part including the bottom surface of the second semiconductor region which is alternately excluded from an upper side part. The first semiconductor region is contacted with both sides of an upper side part and a lower side part of the second semiconductor region.SELECTED DRAWING: Figure 1A | |||
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7 | EP3011594B1 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3011594B1 | Publication Date: 2018-12-26 | Application Number: 14814462.9 | Filing Date: 2014-06-20 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L27/146 | ||||
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8 | US10109662B2 |
Gate-controlled charge modulated device for CMOS image sensors
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Publication/Patent Number: US10109662B2 | Publication Date: 2018-10-23 | Application Number: 14/967,262 | Filing Date: 2015-12-11 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L27/146 | Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | |||
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9 | KR20180029091A |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: KR20180029091A | Publication Date: 2018-03-19 | Application Number: 20187006394 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Kim, Youngsik Na, Yeul Jung, Woo Shik | Assignee: Stratio inc STRATIO | IPC: H01L21/02 | Abstract: 선택적 에피택셜 성장 공정 동안 형성되는 핵을 제거하는 방법은, 하나 이상의 마스크 층을 갖는 기판 위에 하나 이상의 반도체 구조의 제1 그룹을 에피택셜 성장시키는 단계를 포함한다. 복수의 반도체 구조의 제2 그룹은 하나 이상의 마스크 층 상에 형성된다. 방법은, 또한, 하나 이상의 반도체 구조의 제1 그룹 위에 하나 이상의 보호층을 형성하는 단계를 포함한다. 복수의 반도체 구조의 제2 그룹의 적어도 서브세트는 하나 이상의 보호층으로부터 노출된다. 방법은, 하나 이상의 반도체 구조의 제1 그룹 위에 하나 이상의 보호층을 형성하는 단계에 후속하여, 복수의 반도체 구조의 제2 그룹의 적어도 그 서브세트를 에칭하는 단계를 더 포함한다. | |||
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10 | EP3111466A4 |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: EP3111466A4 | Publication Date: 2017-03-29 | Application Number: 16750355 | Filing Date: 2016-05-23 | Inventor： Na, Yeul Jung, Woo-shik Kim, Youngsik Lee, Jae Hyung | Assignee: Stratio inc | IPC: H01L21/20 | ||||
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11 | US2017287706A1 |
Reduction of Surface Roughness in Epitaxially Grown Germanium by Controlled Thermal Oxidation
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Publication/Patent Number: US2017287706A1 | Publication Date: 2017-10-05 | Application Number: 15/624,603 | Filing Date: 2017-06-15 | Inventor： Jung, Woo-shik Na, Yeul Kim, Youngsik Lee, Jae Hyung Lee, Jin Hyung | Assignee: Stratio inc | IPC: H01L21/02 | Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments, the surface roughness is reduced by thermal oxidation of germanium. In some embodiments, the surface roughness is further reduced by controlling a rate of the thermal oxidation. In some embodiments, the surface roughness is reduced by thermal annealing. | |||
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12 | KR20170096134A |
REDUCTION OF SURFACE ROUGHNESS IN EPITAXIALLY GROWN GERMANIUM BY CONTROLLED THERMAL OXIDATION
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Publication/Patent Number: KR20170096134A | Publication Date: 2017-08-23 | Application Number: 20177018942 | Filing Date: 2015-12-15 | Inventor： Lee, Jae Hyung Kim, Youngsik Lee, Jin Hyung Na, Yeul Jung, Woo Shik | Assignee: Stratio inc | IPC: H01L21/02 | Abstract: 본원에서는 게르마늄의 표면 거칠기를 감소시키기 위한 방법들이 개시되어 있다. 몇몇 실시형태에서 | |||
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13 | EP3011594A4 |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS IMAGE SENSORS
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Publication/Patent Number: EP3011594A4 | Publication Date: 2017-03-01 | Application Number: 14814462 | Filing Date: 2014-06-20 | Inventor： Kim, Youngsik Lee, Jae Hyung Na, Yeul Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L27/146 | ||||
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14 | EP3111466A1 |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: EP3111466A1 | Publication Date: 2017-01-04 | Application Number: 16750355.6 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc STRATIO | IPC: H01L21/02 | ||||
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15 | WO2017139008A1 |
BROADBAND VISIBLE-SHORTWAVE INFRARED SPECTROMETER
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Publication/Patent Number: WO2017139008A1 | Publication Date: 2017-08-17 | Application Number: 2016064585 | Filing Date: 2016-12-02 | Inventor： Kim, Youngsik Na, Yeul Jung, Wooshik Kang, Juhyung Lee, Jae Hyung | Assignee: Stratio inc STRATIO | IPC: A61B1/06 | Abstract: An apparatus for analyzing visible and shortwave infrared light includes an input aperture for receiving light that includes a visible wavelength component and a shortwave infrared wavelength component; a first set of one or more lenses configured to relay light from the input aperture; one or more dispersive optical elements configured to disperse light from the first set of one or more lenses; a second set of one or more lenses configured to focus the dispersed light from the one or more dispersive optical elements; and an array detector configured for converting the light from the second set of one or more lenses to electrical signals that include electrical signals indicating intensity of the visible wavelength component and electrical signals indicating intensity of the shortwave infrared wavelength component. | |||
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16 | KR20170029638A |
METHODS FOR REMOVING NUCLEI FORMED DURING EPITAXIAL GROWTH
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Publication/Patent Number: KR20170029638A | Publication Date: 2017-03-15 | Application Number: 20177005543 | Filing Date: 2016-05-23 | Inventor： Lee, Jae Hyung Kim, Youngsik Na, Yeul Jung, Woo Shik | Assignee: Stratio inc STRATIO | IPC: H01L21/02 | Abstract: 선택적 에피택셜 성장 공정 동안 형성되는 핵을 제거하는 방법은 | |||
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17 | US2017195327A1 |
PEER-TO-PEER COMMUNICATION BASED ON DEVICE IDENTIFIERS
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Publication/Patent Number: US2017195327A1 | Publication Date: 2017-07-06 | Application Number: 15/468,027 | Filing Date: 2017-03-23 | Inventor： Lee, Jae Hyung Kim, Youngsik Na, Yeul Jung, Wooshik Bhattiprolu, Seema | Assignee: Stratio inc STRATIO | IPC: H04L29/06 | Abstract: A server system receives from a first electronic device a first device identifier and network information of the first electronic device; subsequent to receiving the first device identifier and the network information of the first electronic device, receives from a second electronic device a second device identifier and network information of the second electronic device; in response to receiving from the second electronic device the second device identifier and the network information of the second electronic device, determines whether the first device identifier is associated with the second device identifier; and, in accordance with a determination that the first device identifier is associated with the second device identifier, sends to the second electronic device the network information of the first electronic device and/or sends to the first electronic device the network information of the second electronic device. | |||
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18 | KR20160021289A |
GATE-CONTROLLED CHARGE MODULATED DEVICE FOR CMOS SENSORS
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Publication/Patent Number: KR20160021289A | Publication Date: 2016-02-24 | Application Number: 20167001437 | Filing Date: 2014-06-20 | Inventor： Lee, Jae Hyung Kim, Youngsik Na, Yeul Jung, Woo Shik | Assignee: Stratio inc | IPC: H01L27/146 | Abstract: 광을 감지하는 디바이스는 제 1 타입의 도펀트로 도핑된 제 1 반도체 영역 및 제 2 타입의 도펀트로 도핑된 제 2 반도체 영역을 포함한다. 제 2 반도체 영역은 제 1 반도체 영역 위에 배치된다. 디바이스는 게이트 절연 층; 게이트 | |||
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19 | US2016099372A1 |
Gate-controlled Charge Modulated Device for CMOS Image Sensors
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Publication/Patent Number: US2016099372A1 | Publication Date: 2016-04-07 | Application Number: 14/967,262 | Filing Date: 2015-12-11 | Inventor： Lee, Jae Hyung Na, Yeul Kim, Youngsik Jung, Woo-shik | Assignee: Stratio inc | IPC: H01L31/113 | Abstract: A device for sensing light includes a first semiconductor region doped with a dopant of a first type and a second semiconductor region doped with a dopant of a second type. The second semiconductor region is positioned above the first semiconductor region. The device includes a gate insulation layer; a gate, a source, and a drain. The second semiconductor region has a top surface that is positioned toward the gate insulation layer and a bottom surface that is positioned opposite to the top surface of the second semiconductor region. The second semiconductor region has an upper portion that includes the top surface of the second semiconductor region and a lower portion that includes the bottom surface of the second semiconductor region and is mutually exclusive with the upper portion. The first semiconductor region is in contact with both the upper portion and the lower portion of the second semiconductor region. | |||
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20 | WO2016100373A1 |
REDUCTION OF SURFACE ROUGHNESS IN EPITAXIALLY GROWN GERMANIUM BY CONTROLLED THERMAL OXIDATION
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Publication/Patent Number: WO2016100373A1 | Publication Date: 2016-06-23 | Application Number: 2015065869 | Filing Date: 2015-12-15 | Inventor： Jung, Woo-shik Lee, Jin Hyung Kim, Youngsik Na, Yeul Lee, Jae Hyung | Assignee: Stratio inc | IPC: H01L21/02 | Abstract: Methods for reducing surface roughness of germanium are described herein. In some embodiments |
3.Current Quota