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1 | US2021074553A1 |
Cross-Wafer RDLs in Constructed Wafers
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Publication/Patent Number: US2021074553A1 | Publication Date: 2021-03-11 | Application Number: 17/087,147 | Filing Date: 2020-11-02 | Inventor： Yu, Chen-hua Kuo, Tin-hao | Assignee: Taiwan semiconductor manufacturing co ltd Taiwan semiconductor manufacturing co ltd | IPC: H01L21/56 | Abstract: A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer. | |||
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2 | US2021005467A1 |
SEMICONDUCTOR MANUFACTURING SYSTEM AND CONTROL METHOD
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Publication/Patent Number: US2021005467A1 | Publication Date: 2021-01-07 | Application Number: 17/027,494 | Filing Date: 2020-09-21 | Inventor： Lin, Su-horng | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L21/67 | Abstract: A system includes a chamber, an inlet valve, a control device, and a recycle pipe. The chamber is configured to perform a semiconductor process and including an output port. The inlet valve is coupled to the chamber and a supply pipe. The controller is coupled to the inlet valve and the chamber. The recycle pipe arranged outside the chamber and coupled to the chamber. The recycle pipe is independent from the supply pipe. The controller is configured to determine whether the chamber is idle, and is configured to control the inlet valve based on the determination of whether the chamber is idle. When the controller closes the output port of the chamber and opens the inlet valve, water from the supply pipe flows into a wall of the chamber through the inlet vale first and then flows into the recycle pipe. | |||
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3 | US2021027984A1 |
MACHINE LEARNING ON WAFER DEFECT REVIEW
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Publication/Patent Number: US2021027984A1 | Publication Date: 2021-01-28 | Application Number: 17/069,712 | Filing Date: 2020-10-13 | Inventor： Chou, Chung-pin Huang, Sheng-wen Liu, Jun-xiu | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01J37/28 | Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques. | |||
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4 | US2021018828A1 |
MASK AND METHOD FOR FORMING THE SAME
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Publication/Patent Number: US2021018828A1 | Publication Date: 2021-01-21 | Application Number: 16/512,795 | Filing Date: 2019-07-16 | Inventor： Lin, Yun-yue | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: G03F1/24 | Abstract: A method of forming a mask includes forming a reflective multilayer over a substrate; forming a capping layer over the reflective multilayer, in which the capping layer includes a ruthenium-containing material and a low carbon solubility material that has a carbon solubility lower than a carbon solubility of the ruthenium-containing material; forming an absorption layer over the capping layer; and etching the absorption layer until exposing the capping layer. | |||
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5 | US2021018849A1 |
SEMICONDUCTOR APPARATUS AND METHOD OF OPERATING THE SAME
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Publication/Patent Number: US2021018849A1 | Publication Date: 2021-01-21 | Application Number: 16/512,767 | Filing Date: 2019-07-16 | Inventor： Chang, Shih-ming Chen, Chiu-hsiang Liu, Ru-gun | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: G03F7/20 | Abstract: A method for taking heat away from the photomask includes driving a working fluid to flow between a photomask and a fluid retaining structure and through a first slit of the fluid retaining structure, such that a boundary of the working fluid is confined between the photomask and the fluid retaining structure; and generating a light to irradiate the photomask through a light transmission region of the fluid retaining structure. | |||
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6 | US2021028095A1 |
Embedded Metal Insulator Metal Structure
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Publication/Patent Number: US2021028095A1 | Publication Date: 2021-01-28 | Application Number: 16/690,535 | Filing Date: 2019-11-21 | Inventor： Kuo, Feng-wei Liao, Wen-shiang | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L23/495 | Abstract: The present disclosure is directed to a method for forming metal insulator metal decoupling capacitors with scalable capacitance. The method can include forming a first redistribution layer with metal lines on a portion of a polymer layer, depositing a photoresist layer on the first redistribution layer, and etching the photoresist layer to form spaced apart first and second TIV openings in the photoresist layer, where the first TIV opening is wider than the second TIV opening. The method can further include depositing a metal in the first and second TIV openings to form respective first and second TIV structures in contact with the metal line, removing the photoresist layer, forming a high-k dielectric on a top surface of the first and second TIV structures, and depositing a metal layer on the high-k dielectric layer to form respective first and second capacitors. | |||
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7 | US2021028208A1 |
PHOTO DIODE WITH DUAL BACKSIDE DEEP TRENCH ISOLATION DEPTH
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Publication/Patent Number: US2021028208A1 | Publication Date: 2021-01-28 | Application Number: 17/070,543 | Filing Date: 2020-10-14 | Inventor： Huang, Yimin | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L27/146 | Abstract: In some embodiments, the present disclosure relates to an image sensor, including a first photodiode and a second photodiode disposed in a semiconductor substrate. A floating diffusion node is disposed along a frontside of the semiconductor substrate and between the first and second photodiodes. A partial backside deep trench isolation (BDTI) structure is disposed within the semiconductor substrate and between the first and second photodiodes. The partial BDTI extends from a backside of the semiconductor substrate and is spaced from the floating diffusion node. A full BDTI structure extends from the backside of the semiconductor substrate to the frontside of the semiconductor substrate. | |||
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8 | US2021020786A1 |
FERROELECTRIC STRUCTURE FOR SEMICONDUCTOR DEVICES
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Publication/Patent Number: US2021020786A1 | Publication Date: 2021-01-21 | Application Number: 16/515,898 | Filing Date: 2019-07-18 | Inventor： Lin, Cheng-ming Yeong, Sai-hooi Fang, Ziwei Young, Bo-feng Chui, Chi On Chang, Chih-yu Chao, Huang-lin | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L29/78 | Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer, | |||
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9 | US2021020770A1 |
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2021020770A1 | Publication Date: 2021-01-21 | Application Number: 16/516,171 | Filing Date: 2019-07-18 | Inventor： Tu, Wen-hsien Lee, Wei-fan | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L29/78 | Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction. | |||
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10 | US2021020633A1 |
SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME
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Publication/Patent Number: US2021020633A1 | Publication Date: 2021-01-21 | Application Number: 17/063,243 | Filing Date: 2020-10-05 | Inventor： Shen, Hsiang-ku Lu, Chih Wei Chen, Hui-chi Yeh, Jeng-ya David | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L27/088 | Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer. | |||
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11 | US2021020642A1 |
Conductive Feature Formation
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Publication/Patent Number: US2021020642A1 | Publication Date: 2021-01-21 | Application Number: 17/062,848 | Filing Date: 2020-10-05 | Inventor： Huang, Yu-lien | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L27/11 | Abstract: The present disclosure provides example embodiments relating to conductive features, and methods of forming the conductive features, that have differing dimensions. In an embodiment, a structure includes a substrate, a dielectric layer over the substrate, and first and second conductive features through the dielectric layer to first and second source/drain regions, respectively, on the substrate. The first conductive feature has a first length along a longitudinal axis of the first conductive feature and a first width perpendicular to the first length. The second conductive feature has a second length along a longitudinal axis of the second conductive feature and a second width perpendicular to the second length. The longitudinal axis of the first conductive feature is aligned with the longitudinal axis of the second conductive feature. The first width is greater than the second width, and the first length is less than the second length. | |||
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12 | US2021020745A1 |
METHOD OF MANUFACTURING A FIELD EFFECT TRANSISTOR USING CARBON NANOTUBES AND A FIELD EFFECT TRANSISTOR
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Publication/Patent Number: US2021020745A1 | Publication Date: 2021-01-21 | Application Number: 16/516,181 | Filing Date: 2019-07-18 | Inventor： Passlack, Matthias Van, Dal Marcus Johannes Henricus Vasen, Timothy Vellianitis, Georgios | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L29/06 | Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT. | |||
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13 | US2021013179A1 |
MODULAR VOLTAGE REGULATORS
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Publication/Patent Number: US2021013179A1 | Publication Date: 2021-01-14 | Application Number: 17/030,420 | Filing Date: 2020-09-24 | Inventor： Samra, Nick Roth, Alan Soenen, Eric Rusu, Stefan Ranucci, Paul | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L25/065 | Abstract: A device includes a semiconductor die. The semiconductor die has formed thereon a plurality of multi-phase voltage regulator modules of the same design formed on a common semiconductor substrate. | |||
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14 | US2021013220A1 |
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
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Publication/Patent Number: US2021013220A1 | Publication Date: 2021-01-14 | Application Number: 16/506,823 | Filing Date: 2019-07-09 | Inventor： Lin, Meng-han Huang, Wen-tuo Tsair, Yong-shiuan | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L27/11531 | Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile. | |||
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15 | US2021050356A1 |
METHOD FOR MANUFACTURING STATIC RANDOM ACCESS MEMORY DEVICE
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Publication/Patent Number: US2021050356A1 | Publication Date: 2021-02-18 | Application Number: 17/005,770 | Filing Date: 2020-08-28 | Inventor： Liaw, Jhon Jhy | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L27/11 | Abstract: In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars. | |||
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16 | US2021050305A1 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
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Publication/Patent Number: US2021050305A1 | Publication Date: 2021-02-18 | Application Number: 17/086,712 | Filing Date: 2020-11-02 | Inventor： Wu, Chi-hsi Chen, Hsien-wei Huang, Li-hsien Yang, Tien-chung | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L23/552 | Abstract: A method includes forming a first semiconductor device, wherein the first semiconductor device includes a top surface and a bottom surface, and wherein the first semiconductor device includes a metal layer having an exposed first surface. The method also includes forming a Electromagnetic Interference (EMI) layer over the top surface and sidewalls of the first semiconductor device, wherein the EMI layer electrically contacts the exposed first surface of the metal layer. The method also includes forming a molding compound over the EMI layer. |
