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1 | US2021005467A1 |
SEMICONDUCTOR MANUFACTURING SYSTEM AND CONTROL METHOD
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Publication/Patent Number: US2021005467A1 | Publication Date: 2021-01-07 | Application Number: 17/027,494 | Filing Date: 2020-09-21 | Inventor： Lin, Su-horng | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L21/67 | Abstract: A system includes a chamber, an inlet valve, a control device, and a recycle pipe. The chamber is configured to perform a semiconductor process and including an output port. The inlet valve is coupled to the chamber and a supply pipe. The controller is coupled to the inlet valve and the chamber. The recycle pipe arranged outside the chamber and coupled to the chamber. The recycle pipe is independent from the supply pipe. The controller is configured to determine whether the chamber is idle, and is configured to control the inlet valve based on the determination of whether the chamber is idle. When the controller closes the output port of the chamber and opens the inlet valve, water from the supply pipe flows into a wall of the chamber through the inlet vale first and then flows into the recycle pipe. | |||
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2 | US10885962B2 |
Vertical memory cells and memory devices using the same
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Publication/Patent Number: US10885962B2 | Publication Date: 2021-01-05 | Application Number: 16/583,029 | Filing Date: 2019-09-25 | Inventor： Mo, Chun-chieh Kuo, Shih-chi | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: G11C11/16 | Abstract: Vertical memory cells and memory devices using the same are disclosed. In one example, a memory cell formed on a backend layer over a substrate is disclosed. The memory cell includes: a first electrode, a second electrode and a magnetic tunnel junction. The first electrode has sidewalls and a bottom surface disposed over the backend layer. The second electrode has sidewalls and a bottom surface in contact with the backend layer. The magnetic tunnel junction is formed between the first electrode and the second electrode. The magnetic tunnel junction is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode. | |||
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3 | US2021004517A1 |
METHOD OF DESIGNING SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2021004517A1 | Publication Date: 2021-01-07 | Application Number: 17/029,985 | Filing Date: 2020-09-23 | Inventor： Wang, Shao-huan Chen, Sheng-hsiung Chen, Wen-hao Chen, Chun-chen Ou, Hung-chih | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: G06F30/394 | Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern. | |||
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4 | US2021004519A1 |
STATIC VOLTAGE DROP (SIR) VIOLATION PREDICTION SYSTEMS AND METHODS
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Publication/Patent Number: US2021004519A1 | Publication Date: 2021-01-07 | Application Number: 17/027,370 | Filing Date: 2020-09-21 | Inventor： Chuang, Yi-lin Lin, Henry Huang, Szu-ju Chen, Yin-an Hong, Amos | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: G06F30/398 | Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout. | |||
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5 | US2021005719A1 |
2D CRYSTAL HETERO-STRUCTURES AND MANUFACTURING METHODS THEREOF
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Publication/Patent Number: US2021005719A1 | Publication Date: 2021-01-07 | Application Number: 17/027,237 | Filing Date: 2020-09-21 | Inventor： Lin, Shih-yen Lee, Si-chen Pan, Samuel C. Chen, Kuan-chao | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L29/24 | Abstract: A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view. | |||
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6 | US10886190B2 |
Devices and methods for heat dissipation of semiconductor integrated circuits
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Publication/Patent Number: US10886190B2 | Publication Date: 2021-01-05 | Application Number: 16/681,687 | Filing Date: 2019-11-12 | Inventor： Yang, Chung-chieh Peng, Yung-chow Hsieh, Chung-peng Liu, Sa-lly | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L29/00 | Abstract: A semiconductor device is disclosed. In one example, the semiconductor device includes: an electronic component having a top surface, a bottom surface, and two end portions; a plurality of contacts disposed on the top surface; and a plurality of metal nodes disposed on the plurality of contacts. The plurality of contacts includes two end contacts disposed at the two end portions respectively and at least one intermediate contact disposed between the two end contacts. The plurality of metal nodes includes two end metal nodes disposed on the two end contacts respectively and at least one intermediate metal node disposed on the at least one intermediate contact. | |||
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7 | US10886269B2 |
Semiconductor device and manufacturing method thereof
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Publication/Patent Number: US10886269B2 | Publication Date: 2021-01-05 | Application Number: 16/133,795 | Filing Date: 2018-09-18 | Inventor： Ching, Kuo-cheng Pan, Kuan-ting Ju, Shi-ning Cheng, Kuan-lun Wang, Chih-hao | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L21/00 | Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin. | |||
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8 | US10886268B2 |
Method of manufacturing a semiconductor device with separated merged source/drain structure
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Publication/Patent Number: US10886268B2 | Publication Date: 2021-01-05 | Application Number: 15/429,844 | Filing Date: 2017-02-10 | Inventor： Lee, Tung Ying Yeh, Chih Chieh Lee, Tsung-lin Yeo, Yee-chia Hsiao, Meng-hsuan | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L29/78 | Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening. | |||
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9 | US10886180B2 |
Semiconductor device with fin end spacer and method of manufacturing the same
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Publication/Patent Number: US10886180B2 | Publication Date: 2021-01-05 | Application Number: 16/426,428 | Filing Date: 2019-05-30 | Inventor： Lee, Tung Ying Wang, Tzu-chung Chang, Kai-tai Yun, Wei-sheng | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L21/8234 | Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer. | |||
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10 | US2021005464A1 |
INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING SAME
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Publication/Patent Number: US2021005464A1 | Publication Date: 2021-01-07 | Application Number: 17/026,712 | Filing Date: 2020-09-21 | Inventor： Lin, Jing-cheng Cheng, Li-hui Tsai, Po-hao | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L21/56 | Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view. | |||
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11 | US2021005734A1 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
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Publication/Patent Number: US2021005734A1 | Publication Date: 2021-01-07 | Application Number: 17/026,562 | Filing Date: 2020-09-21 | Inventor： Lu, Chun-chieh Diaz, Carlos H. Chang, Chih-sheng Peng, Cheng-yi Yeh, Ling-yen | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L29/51 | Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer. | |||
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12 | US2021005595A1 |
Process Control for Package Formation
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Publication/Patent Number: US2021005595A1 | Publication Date: 2021-01-07 | Application Number: 17/026,900 | Filing Date: 2020-09-21 | Inventor： Chen, Ming-fa Chen, Hsien-wei | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L25/00 | Abstract: A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via. | |||
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13 | US10886226B2 |
Conductive contact having staircase barrier layers
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Publication/Patent Number: US10886226B2 | Publication Date: 2021-01-05 | Application Number: 16/050,191 | Filing Date: 2018-07-31 | Inventor： Wu, Chia-yang Jangjian, Shiu-ko Wang, Ting-chun Yu, Yung-si | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L23/532 | Abstract: A semiconductor device includes a transistor having a source/drain and a gate. The semiconductor device also includes a conductive contact for the transistor. The conductive contact provides electrical connectivity to the source/drain or the gate of the transistor. The conductive contact includes a plurality of barrier layers. The barrier layers have different depths from one another. | |||
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14 | US2021005594A1 |
Multi-Stack Package-on-Package Structures
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Publication/Patent Number: US2021005594A1 | Publication Date: 2021-01-07 | Application Number: 17/026,825 | Filing Date: 2020-09-21 | Inventor： Yu, Chen-hua Su, An-jhih | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L25/00 | Abstract: A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein. | |||
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15 | US2021005562A1 |
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
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Publication/Patent Number: US2021005562A1 | Publication Date: 2021-01-07 | Application Number: 17/025,831 | Filing Date: 2020-09-18 | Inventor： Jeng, Shin-puu Chen, Shuo-mao Hsu, Feng-cheng | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L23/00 | Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material. | |||
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16 | US10886182B2 |
Method of manufacturing a semiconductor device and a semiconductor device
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Publication/Patent Number: US10886182B2 | Publication Date: 2021-01-05 | Application Number: 16/427,802 | Filing Date: 2019-05-31 | Inventor： Cheng, Chao-ching Chen, I-sheng Chiang, Hung-li Chen, Tzu-chiang | Assignee: Taiwan semiconductor manufacturing co ltd | IPC: H01L21/8238 | Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers containing Ge and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A Ge concentration in the first semiconductor layers is increased. A sacrificial gate structure is formed over the fin structure. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed. The second semiconductor layers in a channel region are removed, thereby releasing the first semiconductor layers in which the Ge concentration is increased. A gate structure is formed around the first semiconductor layers in which the Ge concentration is increased. |
