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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US202051791A1
Etch Process With Rotatable Shower Head
Publication/Patent Number: US202051791A1 Publication Date: 2020-02-13 Application Number: 20/191,665 Filing Date: 2019-10-18 Inventor: Chang, Hung-jui   Chiu, Yi-wei   Lin, Yu-chi   Lin, Chin-hsing   Ke, Yu-lun   Assignee: Taiwan semiconductor manufacturing co ltd   Taiwan semiconductor manufacturing co ltd   IPC: H01L21/683 Abstract: The present disclosure describes an exemplary etch process in a reactor that includes a shower head and an electrostatic chuck configured to receive a radio frequency (RF) power. The shower head includes a top plate and a bottom plate with one or more gas channels that receive incoming gases. The method can include (i) rotating the top plate or the bottom plate of the shower head to a first position to allow a gas to flow through the shower head; (ii) performing a surface modification cycle that includes: applying a negative direct current (DC) bias voltage to the shower head, applying an RF power signal to the wafer chuck; and (iii) performing an etching cycle that includes: removing the negative DC bias voltage from the shower head and lowering the RF power signal applied to the wafer chuck.
2 US202020371A1
BOOST BYPASS CIRCUITRY IN A MEMORY STORAGE DEVICE
Publication/Patent Number: US202020371A1 Publication Date: 2020-01-16 Application Number: 20/191,650 Filing Date: 2019-07-03 Inventor: Chen, Yen-huei   Fujiwara, Hidehiro   Assignee: Taiwan semiconductor manufacturing co ltd   Taiwan semiconductor manufacturing co ltd   IPC: H03K19/003 Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.
3 US2020278604A1
LITHOGRAPHY MODEL CALIBRATION
Publication/Patent Number: US2020278604A1 Publication Date: 2020-09-03 Application Number: 16/748,551 Filing Date: 2020-01-21 Inventor: Lo, Shih-hsiang   Huang, Hsu-ting   Liu, Ru-gun   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: G03F1/36 Abstract: Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.
4 US10763280B2
Hybrid FinFET structure
Publication/Patent Number: US10763280B2 Publication Date: 2020-09-01 Application Number: 15/990,278 Filing Date: 2018-05-25 Inventor: Liu, Chien-chen   Shen, Guan-jie   Chang, Chia-der   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L27/12 Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) device, the first FinFET device including a plurality of fins formed in a substrate, an epitaxial layer of semiconductor material formed on the fins forming non-planar source/drain regions, and a first gate structure traversing across the plurality of fins. The semiconductor device includes a second FinFET device, the second FinFET device including a substantially planar fin formed in the substrate, an epitaxial layer of the semiconductor material formed on the substantially planar fin and forming substantially planar source/drain regions, and a second gate structure traversing across the substantially planar fin.
5 US10763140B2
Semiconductor processing station
Publication/Patent Number: US10763140B2 Publication Date: 2020-09-01 Application Number: 16/159,709 Filing Date: 2018-10-14 Inventor: Lu, Chia-wei   Huang, Hon-lin   Wang, Hung-chih   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: B05C13/00 Abstract: A semiconductor processing station including a central transfer chamber, a load lock chamber disposed adjacent to the central transfer chamber, and a cooling stage disposed adjacent to the load lock chamber and the central transfer chamber is provided. The load lock chamber is adapted to contain a wafer carrier including a plurality of wafers. The central transfer chamber communicates between the cooling stage and the load lock chamber to transfer a wafer of the plurality of wafers between the cooling stage and the load lock chamber.
6 US10763255B2
Semiconductor device and manufacturing method thereof
Publication/Patent Number: US10763255B2 Publication Date: 2020-09-01 Application Number: 16/103,721 Filing Date: 2018-08-14 Inventor: Ching, Kuo-cheng   Ju, Shi-ning   Wang, Chih-hao   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L27/088 Abstract: A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.
7 US10763168B2
Semiconductor structure with doped via plug and method for forming the same
Publication/Patent Number: US10763168B2 Publication Date: 2020-09-01 Application Number: 16/021,216 Filing Date: 2018-06-28 Inventor: Hsieh, Tung-po   Liu, Su-hao   Liu, Hong-chih   Huang, Jing-huei   Huang, Jie-huang   Tan, Lun-kuang   Chang, Huicheng   Chen, Liang-yin   Chen, Kuo-ju   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L21/768 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.
8 US2020279854A1
Cutting Metal Gates in Fin Field Effect Transistors
Publication/Patent Number: US2020279854A1 Publication Date: 2020-09-03 Application Number: 16/876,525 Filing Date: 2020-05-18 Inventor: Yin, Li-wei   Ku, Shu-yuan   Cheng, Chun-fai   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L27/11 Abstract: A semiconductor structure includes a first metal gate disposed over a first device region of a semiconductor substrate, where the first metal gate includes a first work function metal layer, a second metal gate disposed over a second device region of the semiconductor substrate, where the second metal gate includes a second work function metal layer, a first gate cut feature separating the first metal gate, where sidewalls of the first gate cut feature are defined by the first work function metal layer and a bulk conductive layer, and a second gate cut feature separating the second metal gate, where sidewalls of the second gate cut feature are defined by the second work function metal layer but not by the bulk conductive layer.
9 US2020279778A1
Etch Profile Control of Polysilicon Structures of Semiconductor Devices
Publication/Patent Number: US2020279778A1 Publication Date: 2020-09-03 Application Number: 16/877,345 Filing Date: 2020-05-18 Inventor: Ching, Kuo-cheng   Wang, Chih-hao   Pan, Kuan-ting   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L21/8234 Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively
10 US2020279774A1
SEMICONDUCTOR DEVICES
Publication/Patent Number: US2020279774A1 Publication Date: 2020-09-03 Application Number: 16/876,127 Filing Date: 2020-05-18 Inventor: Su, Fu-hsiang   Chen, Jyh-huei   Tsai, Kuo-chiang   Yu, Ke-jing   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L21/768 Abstract: A semiconductor device includes a substrate, a first gate structure and a second gate structure over the substrate, a first hard mask on a top surface of the first gate structure, a second hard mask on the second gate structure and a third hard mask disposed between the first gate structure and the second gate structure and disposed between the first hard mask and the second hard mask. A bottom surface of the third hard mask is substantially flush with a bottom surface of the first gate structure.
11 US2020279920A1
EPITAXIAL GROWTH METHODS AND STRUCTURES THEREOF
Publication/Patent Number: US2020279920A1 Publication Date: 2020-09-03 Application Number: 15/929,722 Filing Date: 2020-05-18 Inventor: Ueno, Tetsuji   Yu, Ming-hua   Yang, Chan-lon   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L29/167 Abstract: A method and structure for providing a two-step defect reduction bake, followed by a high-temperature epitaxial layer growth. In various embodiments, a semiconductor wafer is loaded into a processing chamber. While the semiconductor wafer is loaded within the processing chamber, a first pre-epitaxial layer deposition baking process is performed at a first pressure and first temperature. In some cases, after the first pre-epitaxial layer deposition baking process, a second pre-epitaxial layer deposition baking process is then performed at a second pressure and second temperature. In some embodiments, the second pressure is different than the first pressure. By way of example, after the second pre-epitaxial layer deposition baking process and while at a growth temperature, a precursor gas may then be introduced into the processing chamber to deposit an epitaxial layer over the semiconductor wafer.
12 US10761927B2
Detection and correction of data bit errors using error correction codes
Publication/Patent Number: US10761927B2 Publication Date: 2020-09-01 Application Number: 16/128,967 Filing Date: 2018-09-12 Inventor: Lu, Shih-lien Linus   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: G06F11/10 Abstract: A method of correcting one or more bit errors in a memory device includes retrieving a codeword from a memory device. The codeword includes a data and an error correcting code. The method further includes determining whether the one or more bit errors are present in the retrieved codeword and correcting the retrieved codeword for the one bit error in response to determining one bit error is present in the retrieved codeword. The method also includes flipping a bit of the retrieved codeword in response to determining a plurality of bit errors is present in the retrieved codeword and correcting the retrieved codeword for the plurality of bit errors based on the bit-flipped codeword.
13 US10762960B2
Resistive random access memory device
Publication/Patent Number: US10762960B2 Publication Date: 2020-09-01 Application Number: 16/158,498 Filing Date: 2018-10-12 Inventor: Chih, Yu-der   Chou, Chung-cheng   Chu, Wen-ting   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: G11C11/00 Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
14 US10770131B2
SRAM cell for interleaved wordline scheme
Publication/Patent Number: US10770131B2 Publication Date: 2020-09-08 Application Number: 16/376,198 Filing Date: 2019-04-05 Inventor: Fujiwara, Hidehiro   Liao, Hung-jen   Pan, Hsien-yu   Chen, Yen-huei   Sinangil, Mahmut   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: G11C11/412 Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
15 US10756174B2
Multiple-stacked semiconductor nanowires and source/drain spacers
Publication/Patent Number: US10756174B2 Publication Date: 2020-08-25 Application Number: 15/613,339 Filing Date: 2017-06-05 Inventor: Van, Dal Mark   Doornbos, Gerben   Lin, Chung-te   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L21/82 Abstract: A semiconductor device includes a substrate, a gate structure, at least one nanowire, at least one epitaxy structure, and at least one source/drain spacer. The gate structure is disposed on the substrate. The nanowire extends through the gate structure. The epitaxy structure is disposed on the substrate and is in contact with the nanowire. The source/drain spacer is disposed between the epitaxy structure and the gate structure and is embedded in the epitaxy structure.
16 US10756258B2
Memory device and fabrication method thereof
Publication/Patent Number: US10756258B2 Publication Date: 2020-08-25 Application Number: 15/860,566 Filing Date: 2018-01-02 Inventor: Liao, Wei-hao   Tien, Hsi-wen   Lu, Chih-wei   Dai, Pin-ren   Lee, Chung-ju   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L43/12 Abstract: A method for fabricating a memory device includes forming a bottom electrode over a substrate; forming an etch stop layer over and surrounding the bottom electrode; removing at least one portion of the etch stop layer to expose the bottom electrode; forming a stack layer over the bottom electrode and a remaining portion of the etch stop layer, the stack layer comprising a resistance switching layer; and etching the stack layer to form a stack over the bottom electrode, the stack comprising a resistance switching element over the bottom electrode and a top electrode over the resistance switching element, wherein the etch stop layer has a higher etch resistance to the etching than that of the resistance switching element.
17 US2020273966A1
Dual Metal Via for Contact Resistance Reduction
Publication/Patent Number: US2020273966A1 Publication Date: 2020-08-27 Application Number: 16/870,360 Filing Date: 2020-05-08 Inventor: Cheng, Chung-liang   Chen, Yen-yu   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L29/66 Abstract: A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.
18 US2020273910A1
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020273910A1 Publication Date: 2020-08-27 Application Number: 16/283,455 Filing Date: 2019-02-22 Inventor: Wu, Jau-yi   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L27/24 Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a substrate. A bottom electrode via opening is formed in the dielectric layer. A bottom electrode is formed in the bottom electrode via opening. The bottom electrode is etched back. A selector is formed in the bottom electrode via opening and over the bottom electrode. A memory layer is formed over the selector. A top electrode is formed over the memory layer.
19 US2020273964A1
METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING GATE-ALL-AROUND STRUCTURE WITH INNER SPACER LAST PROCESS
Publication/Patent Number: US2020273964A1 Publication Date: 2020-08-27 Application Number: 16/282,214 Filing Date: 2019-02-21 Inventor: Lin, Chun-hsiung   Wang, Pei-hsun   Wang, Chih-hao   Ching, Kuo-cheng   Huang, Jui-chien   Assignee: Taiwan semiconductor manufacturing co ltd   IPC: H01L29/66 Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.
20 US2020270121A1