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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10666578B2
Network-on-chip system and a method of generating the same
Publication/Patent Number: US10666578B2 Publication Date: 2020-05-26 Application Number: 15/257,210 Filing Date: 2016-09-06 Inventor: Venugopalan, Ravi   Goel, Sandeep Kumar   Lee, Yun-han   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H04L12/933 Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
2 US10699766B2
Word-line driver and method of operating a word-line driver
Publication/Patent Number: US10699766B2 Publication Date: 2020-06-30 Application Number: 16/590,869 Filing Date: 2019-10-02 Inventor: Taghvaei, Ali   Katoch, Atul   Assignee: Taiwan semiconductor manufacturing company limited   IPC: G11C5/06 Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.
3 US2020058765A1
Method of Forming MOSFET Structure
Publication/Patent Number: US2020058765A1 Publication Date: 2020-02-20 Application Number: 16/665,011 Filing Date: 2019-10-28 Inventor: Fu, Ching-feng   Yen, Yu-chan   Ko, Chih-hsin   Lee, Chun-hung   Lin, Huan-just   Chang, Hui-cheng   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H01L29/66 Abstract: Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.
4 US2020066685A1
Structures for Providing Electrical Isolation in Semiconductor Devices
Publication/Patent Number: US2020066685A1 Publication Date: 2020-02-27 Application Number: 16/667,985 Filing Date: 2019-10-30 Inventor: Chern, Chan-hong   Chen, Mark   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H01L25/07 Abstract: Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
5 US2020051836A1
Systems and Methods for Annealing Semiconductor Structures
Publication/Patent Number: US2020051836A1 Publication Date: 2020-02-13 Application Number: 16/658,312 Filing Date: 2019-10-21 Inventor: Tsai, Chun-hsiung   Fang, Zi-wei   Wang, Chao-hsiung   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H01L21/67 Abstract: Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation.
6 US2020019673A1
System and Method for Calculating Cell Edge Leakage
Publication/Patent Number: US2020019673A1 Publication Date: 2020-01-16 Application Number: 16/581,858 Filing Date: 2019-09-25 Inventor: Peng, Shih-wei   Young, Charles Chew-yuen   Tzeng, Jiann-tyng   Sio, Kam-tou   Assignee: Taiwan semiconductor manufacturing company limited   IPC: G06F17/50 Abstract: A method for calculating cell edge leakage in a semiconductor device comprising performing a device leakage simulation to obtain leakage information for different cell edge conditions and providing attributes associated with cell edges in the semiconductor device. The method further comprises performing an analysis to identify cell abutment cases present in the semiconductor device and calculating the leakage of the semiconductor device based at least in part on probabilities associated with the cell abutment cases and the simulated leakage values obtained from the device leakage simulation.
7 US2020243510A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020243510A1 Publication Date: 2020-07-30 Application Number: 16/848,925 Filing Date: 2020-04-15 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Chao, Yi-ping   Lee, Chih-lin   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
8 US2020136640A1
Low Distortion Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) and Associated Methods
Publication/Patent Number: US2020136640A1 Publication Date: 2020-04-30 Application Number: 16/708,701 Filing Date: 2019-12-10 Inventor: Chuang, Mei-chen   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H03M1/46 Abstract: An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=N*VDD, where N<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where Vref=N*VDD, where N<1, wherein the first capacitor having a capacitive value that is equal to (1−N) times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (VIN) signal as the second input to the comparator.
9 US2020143875A1
Write Assist for a Memory Device and Methods of Forming the Same
Publication/Patent Number: US2020143875A1 Publication Date: 2020-05-07 Application Number: 16/734,651 Filing Date: 2020-01-06 Inventor: Singh, Sahil Preet   Chen, Yen-huei   Liao, Hung-jen   Assignee: Taiwan semiconductor manufacturing company limited   IPC: G11C11/419 Abstract: A semiconductor memory device includes an array of memory cells arranged in a plurality of rows and columns, with each memory cell including a plurality of bit cell transistors. The semiconductor memory device further includes a plurality of write assist circuits, including one or more write assist circuits within each column of the array of memory cells, each write assist circuit configured to provide a core voltage to memory cells within the same column and to reduce the core voltage during a write operation. The array of memory cells and the plurality of write assist circuits have a common semiconductor layout.
10 US10680078B2
Semiconductor arrangement and formation thereof
Publication/Patent Number: US10680078B2 Publication Date: 2020-06-09 Application Number: 16/240,887 Filing Date: 2019-01-07 Inventor: Yang, Tai-i   Lin, Tien-lu   Lien, Wai-yi   Wang, Chih-hao   Wu, Jiun-peng   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H01L21/02 Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.
11 US2020040450A1
System and Method for Supplying a Precursor for an Atomic Layer Deposition (ALD) Process
Publication/Patent Number: US2020040450A1 Publication Date: 2020-02-06 Application Number: 16/600,648 Filing Date: 2019-10-14 Inventor: Hsieh, Bor-chiuan   Huang, Chien-kuo   Huang, Tai-chun   Hsu, Kuang-yuan   Lee, Tze-liang   Assignee: Taiwan semiconductor manufacturing company limited   IPC: C23C16/44 Abstract: Systems and methods for supplying a precursor material for an atomic layer deposition (ALD) process are provided. A gas supply provides one or more precursor materials to a deposition chamber. The deposition chamber receives the one or more precursor materials via an input line. A gas circulation system is coupled to an output line of the deposition chamber. The gas circulation system includes a gas composition detection system configured to produce an output signal indicating a composition of a gas exiting the deposition chamber through the output line. The gas circulation system also includes a circulation line configured to transport the gas exiting the deposition chamber to the input line. A controller is coupled to the gas supply. The controller controls the providing of the one or more precursor materials by the gas supply based on the output signal of the gas composition detection system.
12 US2020131662A1
MAGNETIC STRUCTURE FOR METAL PLATING CONTROL
Publication/Patent Number: US2020131662A1 Publication Date: 2020-04-30 Application Number: 16/731,169 Filing Date: 2019-12-31 Inventor: Tsai, Ming-chin   Kao, Chung-en   Lu, Victor Y.   Assignee: Taiwan semiconductor manufacturing company limited   IPC: C25D17/00 Abstract: Among other things, one or more systems and techniques for promoting metal plating profile uniformity are provided. A magnetic structure is positioned relative to a semiconductor wafer that is to be electroplated with metal during a metal plating process. In an embodiment, the magnetic structure applies a force that decreases an edge plating current by moving metal ions away from a wafer edge of the semiconductor wafer. In an embodiment, the magnetic structure applies a force that increases a center plating current by moving metal ions towards a center portion of the semiconductor wafer. In this way, the edge plating current has a current value that is similar to a current value of the center plating current. The similarity between the center plating current and the edge plating current promotes metal plating uniformity.
13 US2020244270A1
Segmentation Superposition Technique for Binary Error Compensation
Publication/Patent Number: US2020244270A1 Publication Date: 2020-07-30 Application Number: 16/851,548 Filing Date: 2020-04-17 Inventor: Li, Chao Chieh   Liao, Chia-chun   Yuan, Min-shueh   Staszewski, Robert Bogdan   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H03L1/02 Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.
14 US2020110913A1
RC Tool Accuracy Time Reduction
Publication/Patent Number: US2020110913A1 Publication Date: 2020-04-09 Application Number: 16/709,044 Filing Date: 2019-12-10 Inventor: Wu, Hui-i   Su, Ke-ying   Lo, Wan-ting   Vepuri, Niranjan   Chang, Hsiang-ho   Assignee: Taiwan semiconductor manufacturing company limited   IPC: G06F30/35 Abstract: Fabricating a first semiconductor device cell using a first process based on a first process parameter or material comprises extracting semiconductor device parameters from the first process parameters to obtain extracted semiconductor device parameters of a first semiconductor device cell. The fabrication process includes training an artificial intelligence to obtain a predictive artificial intelligence using training data as input, the training data comprising the extracted semiconductor device cell parameters and the first process parameter or material. A proposed process modification is provided to the predictive artificial intelligence to generate a predicted cell delay by the predictive artificial intelligence. The predicted cell delay is evaluated against a cell delay threshold. When the predicted cell delay satisfies the cell delay threshold, a new semiconductor device cell is fabricated using a modified process incorporating the proposed process modification.
15 US2020227126A1
Memory Device with a Fuse Protection Circuit
Publication/Patent Number: US2020227126A1 Publication Date: 2020-07-16 Application Number: 16/830,429 Filing Date: 2020-03-26 Inventor: Chih, Yu-der   Hung, Chen-ming   Tseng, Jen-chou   Lee, Jam-wem   Song, Ming-hsiang   Lee, Shu-chuan   Chou, Shao-yu   Su, Yu-ti   Assignee: Taiwan semiconductor manufacturing company limited   IPC: G11C17/18 Abstract: A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a program line and a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
16 US202018642A1
Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing
Publication/Patent Number: US202018642A1 Publication Date: 2020-01-16 Application Number: 20/191,645 Filing Date: 2019-06-27 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Lee, Chih-lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H03L7/081 Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.
17 US202044680A1
Systems and Methods for Die-to-Die Communication
Publication/Patent Number: US202044680A1 Publication Date: 2020-02-06 Application Number: 20/191,660 Filing Date: 2019-10-14 Inventor: Jou, Chewn-pu   Chen, Huan-neng   Shen, William Wu   Kuo, Feng-wei   Cho, Lan-chou   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H04L1/18 Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.
18 US2020035288A1
Word-Line Driver and Method of Operating a Word-Line Driver
Publication/Patent Number: US2020035288A1 Publication Date: 2020-01-30 Application Number: 16/590,869 Filing Date: 2019-10-02 Inventor: Taghvaei, Ali   Katoch, Atul   Assignee: Taiwan semiconductor manufacturing company limited   IPC: G11C11/40 Abstract: Word-line drivers, memories, and methods of operating word-line drivers are provided. A word-line driver coupled to an array of memory cells includes a decoder powered by a first power supply. The decoder is configured to decode an address to provide a plurality of word-line signals. The word-line driver also includes a plurality of output stages powered by a second power supply that is different than the first power supply. Each of the output stages includes a first transistor having a gate controlled by a first control signal and an inverter. The inverter is coupled between the first transistor and a ground and has an input coupled to the decoder to receive one of the word-line signals. The word-line driver also includes pull-down circuitry coupled between the gates of the first transistors and the ground and activated by a second control signal.
19 US2020111887A1
METHOD OF FORMING A VERTICAL DEVICE
Publication/Patent Number: US2020111887A1 Publication Date: 2020-04-09 Application Number: 16/706,958 Filing Date: 2019-12-09 Inventor: Chen, De-fang   Tsai, Teng-chun   Lin, Cheng-tung   Wang, Li-ting   Lee, Chun-hung   Chang, Ming-ching   Lin, Huan-just   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H01L29/66 Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
20 US2020135468A1
Methods and Systems for Dopant Activation Using Microwave Radiation
Publication/Patent Number: US2020135468A1 Publication Date: 2020-04-30 Application Number: 16/726,438 Filing Date: 2019-12-24 Inventor: Tsai, Chun-hsiung   Yang, Huai-tei   Yu, Kuo-feng   Chen, Kei-wei   Assignee: Taiwan semiconductor manufacturing company limited   IPC: H01L21/268 Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction.