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    Total 26532 results Used time 0.174 s
    No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
    		Application Number Application Number Filing Date Filing Date
    		Inventor Inventor Assignee Assignee IPC IPC
    1 US10658409B2
    Semiconductor structure and method of manufacturing the same
    		Publication/Patent Number: US10658409B2 Publication Date: 2020-05-19 Application Number: 15/903,560 Filing Date: 2018-02-23 Inventor： Li, Sheng-chan   Chen, I-nan   Chen, Tzu-hsiang   Wang, Yu-jen   Chiang, Yen-ting   Chou, Cheng-hsien   Tsai, Cheng-yuan   Assignee: Taiwan semiconductor manufacturing company ltd u   IPC: H01L27/146 Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.
    2 US10704158B2
    Electrochemical plating
    		Publication/Patent Number: US10704158B2 Publication Date: 2020-07-07 Application Number: 15/376,060 Filing Date: 2016-12-12 Inventor： Lien, Chen-kuang   Chiu, Lun-chieh   Chang, Yu-min   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: C25D21/12 Abstract: Methods for use in electrochemical plating processes are described herein. An exemplary method includes determining a wafer electrical property associated with a wafer, wherein the wafer electrical property affects the wafer during an electrochemical plating (ECP) process; adjusting a process parameter to be applied to the wafer during the ECP process based on the determined wafer electrical property, wherein the process parameter specifies at least one of a current or a voltage; and applying the adjusted process parameter to the wafer undergoing the ECP process. In some implementations, the process parameter is adjusted, such that a peak entry current of the ECP process substantially matches a plating current of the ECP process induced following the peak entry current.
    3 US10727319B2
    Dislocation SMT for FinFET device
    		Publication/Patent Number: US10727319B2 Publication Date: 2020-07-28 Application Number: 15/430,063 Filing Date: 2017-02-10 Inventor： Lo, Wen-cheng   Chang, Sun-jay   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L27/12 Abstract: Stress memorization techniques (SMTs) for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a capping layer over a fin structure; forming an amorphous region within the fin structure while the capping layer is disposed over the fin structure; and performing an annealing process to recrystallize the amorphous region. The capping layer enables the fin structure to retain stress effects induced by forming the amorphous region and/or performing the annealing process.
    4 EP3534422B1
    MULTIPLY SPIN-COATED ULTRA-THICK HYBRID HARD MASK FOR SUB 60NM MRAM DEVICES
    		Publication/Patent Number: EP3534422B1 Publication Date: 2020-09-09 Application Number: 19157883.0 Filing Date: 2019-02-18 Inventor： Yi, Yang   Yu-jen, Wang   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L43/12
    5 US2020135574A1
    SEMICONDUCTOR DEVICE AND METHOD
    		Publication/Patent Number: US2020135574A1 Publication Date: 2020-04-30 Application Number: 16/290,760 Filing Date: 2019-03-01 Inventor： Yang, Cheng-yu   Yang, Feng-cheng   Lee, Wei-yang   Chen, Yen-ming   Chen, Yen-ting   Assignee: Taiwan semiconductor manufacturing company ltd   Taiwan semiconductor manufacturing company ltd   IPC: H01L21/8234 Abstract: A semiconductor device including a fin field effect transistor (FinFET) with a cut metal gate (CMG) and a method of manufacturing the semiconductor device are described herein. The method includes forming a CMG protective helmet structure at a top portion of a CMG dummy gate plug formed within a semiconductor substrate. The CMG protective helmet structure prevents consumption and damage of a dummy filler material in a CMG region and prevents undesirable polymer/residue byproducts from forming on top surfaces of epitaxial regions of the FinFET during etching processes.
    6 US2020117874A1
    Fingerprint Sensor Device and Method
    		Publication/Patent Number: US2020117874A1 Publication Date: 2020-04-16 Application Number: 16/710,478 Filing Date: 2019-12-11 Inventor： Yu, Chen-hua   Chen, Yu-feng   Chen, Chih-hua   Tsai, Hao-yi   Liu, Chung-shi   Assignee: Taiwan semiconductor manufacturing company ltd   Taiwan semiconductor manufacturing company ltd   IPC: G06K9/00 Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    7 US10770290B2
    Method for forming stacked nanowire transistors
    		Publication/Patent Number: US10770290B2 Publication Date: 2020-09-08 Application Number: 16/033,401 Filing Date: 2018-07-12 Inventor： Lee, Tung Ying   Yu, Shao-ming   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L21/02 Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.
    8 US10727061B2
    Method for integrated circuit patterning
    		Publication/Patent Number: US10727061B2 Publication Date: 2020-07-28 Application Number: 15/947,287 Filing Date: 2018-04-06 Inventor： Yang, Tsung-lin   Chen, Hua Feng   Chen, Kuei-shun   Hsieh, Min-yann   Li, Po-hsueh   Fu, Shih-chi   Lung, Yuan-hsiang   Tsai, Yan-tso   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L21/265 Abstract: An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.
    9 US10741688B2
    Structure and method for integrated circuit
    		Publication/Patent Number: US10741688B2 Publication Date: 2020-08-11 Application Number: 15/803,238 Filing Date: 2017-11-03 Inventor： Kuang, Shin-jiun   Yu, Tsung-hsing   Sheu, Yi-ming   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L29/78 Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    10 US2020066972A1
    Self-Aligned Encapsulation Hard Mask to Separate Physically Under-Etched MTJ Cells to Reduce Conductive R-Deposition
    		Publication/Patent Number: US2020066972A1 Publication Date: 2020-02-27 Application Number: 16/113,079 Filing Date: 2018-08-27 Inventor： Yang, Yi   Shen, Dongna   Sundar, Vignesh   Wang, Yu-jen   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L43/12 Abstract: A method for etching a magnetic tunneling junction (MTJ) structure is described. A MTJ stack is deposited on a bottom electrode wherein the MTJ stack comprises at least a pinned layer, a barrier layer on the pinned layer, and a free layer on the barrier layer, A top electrode layer is deposited on the MTJ stack. A hard mask is deposited on the top electrode layer. The top electrode layer and hard mask are etched. Thereafter, the MTJ stack not covered by the hard mask is etched, stopping at or within the pinned layer. Thereafter, an encapsulation layer is deposited over the partially etched MTJ stack and etched away on horizontal surfaces leaving a self-aligned hard mask on sidewalls of the partially etched MTJ stack. Finally, the remaining MTJ stack not covered by hard mask and self-aligned hard mask is etched to complete the MTJ structure.
    11 US10770588B2
    (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor device
    		Publication/Patent Number: US10770588B2 Publication Date: 2020-09-08 Application Number: 15/225,298 Filing Date: 2016-08-01 Inventor： Cheng, Chao-ching   Ko, Chih-hsin   Wann, Hsingjen   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L29/78 Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
    12 US2020111744A1
    Interconnect Structure and Method of Forming Same
    		Publication/Patent Number: US2020111744A1 Publication Date: 2020-04-09 Application Number: 16/707,450 Filing Date: 2019-12-09 Inventor： Sung, Su-jen   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L23/535 Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.
    13 US10763292B2
    Interconnect apparatus and method for a stacked semiconductor device
    		Publication/Patent Number: US10763292B2 Publication Date: 2020-09-01 Application Number: 16/224,300 Filing Date: 2018-12-18 Inventor： Lin, Jeng-shyan   Tsai, Shu-ting   Yaung, Dun-nian   Liu, Jen-cheng   Hung, Feng-chi   Chou, Shih-pei   Kao, Min-feng   Chen, Szu-ying   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L27/146 Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.
    14 US2020286782A1
    Method of Semiconductor Integrated Circuit Fabrication
    		Publication/Patent Number: US2020286782A1 Publication Date: 2020-09-10 Application Number: 16/880,718 Filing Date: 2020-05-21 Inventor： Shieh, Ming-feng   Hsieh, Hung-chang   Tseng, Wen-hung   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L21/768 Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.
    15 US10535566B2
    Semiconductor device and method of manufacture
    		Publication/Patent Number: US10535566B2 Publication Date: 2020-01-14 Application Number: 15/420,280 Filing Date: 2017-01-31 Inventor： Chen, Hung-hao   Chang, Che-cheng   Tseng, Horng-huei   Chen, Wen-tung   Liu, Yu-cheng   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L21/8234 Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.
    16 US10535616B2
    Warpage control in package-on-package structures
    		Publication/Patent Number: US10535616B2 Publication Date: 2020-01-14 Application Number: 16/233,667 Filing Date: 2018-12-27 Inventor： Chen, Wei-yu   Hu, Yu-hsiang   Lin, Wei-hung   Cheng, Ming-da   Liu, Chung-shi   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L23/00 Abstract: A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate.
    17 US10527788B2
    Package structure and methods of forming same
    		Publication/Patent Number: US10527788B2 Publication Date: 2020-01-07 Application Number: 16/361,750 Filing Date: 2019-03-22 Inventor： Lai, Jui Hsieh   Kuo, Ying-hao   Chen, Hai-ching   Bao, Tien-i   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: G02B6/12 Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.
    18 US10622302B2
    Via for semiconductor device connection and methods of forming the same
    		Publication/Patent Number: US10622302B2 Publication Date: 2020-04-14 Application Number: 16/121,360 Filing Date: 2018-09-04 Inventor： Yu, Chen-hua   Su, An-jhih   Wu, Chi-hsi   Chiou, Wen-chih   Wu, Tsang-jiuh   Yeh, Der-chyang   Yeh, Ming Shih   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L23/522 Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    19 US10622297B2
    Semiconductor device and method
    		Publication/Patent Number: US10622297B2 Publication Date: 2020-04-14 Application Number: 16/200,029 Filing Date: 2018-11-26 Inventor： Lin, Jing-cheng   Wu, Chi-hsi   Yu, Chen-hua   Tsai, Po-hao   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L21/00 Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.
    20 US10636908B2
    Method of removing an etch mask
    		Publication/Patent Number: US10636908B2 Publication Date: 2020-04-28 Application Number: 16/206,348 Filing Date: 2018-11-30 Inventor： Chu, Chun-han   Chen, Nai-chia   Huang, Ping-jung   Chuo, Tsung-min   Shih, Jui-ming   Yen, Bi-ming   Assignee: Taiwan semiconductor manufacturing company ltd   IPC: H01L21/02 Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.