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1 | US2021043253A1 |
MEMORY COMPUTATION CIRCUIT AND METHOD
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Publication/Patent Number: US2021043253A1 | Publication Date: 2021-02-11 | Application Number: 17/077,401 | Filing Date: 2020-10-22 | Inventor： Chen, Yen-huei Liao, Hung-jen Chang, Jonathan Tsung-yung Fujiwara, Hidehiro | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD | IPC: G11C11/419 | Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit. | |||
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2 | US2021035993A1 |
FeRAM Decoupling Capacitor
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Publication/Patent Number: US2021035993A1 | Publication Date: 2021-02-04 | Application Number: 16/780,418 | Filing Date: 2020-02-03 | Inventor： Chen, Tzu-yu Tu, Kuo-chi Chang, Fu-chen Chang, Chih-hsiang Shih, Sheng-hung | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd | IPC: H01L27/11507 | Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider. | |||
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3 | US10943645B2 |
Memory device with a booster word line
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Publication/Patent Number: US10943645B2 | Publication Date: 2021-03-09 | Application Number: 16/515,503 | Filing Date: 2019-07-18 | Inventor： Hong, Hyunsung | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD | IPC: G11C11/418 | Abstract: A semiconductor device is provided. The semiconductor includes a plurality of memory cells arranged in rows and columns. The device further includes a plurality of primary word lines, each being connected to a first plurality of memory cells arranged in a row and a plurality of bit line pairs, each being connected to a second plurality of memory cells arranged in a column. The device further includes a word line driver circuit operative to select a first primary word line of the plurality of primary word lines and charge the selected first primary word line from a first end and a secondary word line operative to charge the selected first primary word line from a second end. | |||
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4 | US10923355B2 |
Methods and systems for dopant activation using microwave radiation
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Publication/Patent Number: US10923355B2 | Publication Date: 2021-02-16 | Application Number: 16/726,438 | Filing Date: 2019-12-24 | Inventor： Tsai, Chun-hsiung Yang, Huai-tei Yu, Kuo-feng Chen, Kei-wei | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD | IPC: H01L21/268 | Abstract: A semiconductor structure includes a substrate, a source/drain (S/D) junction, and an S/D contact. The S/D junction is associated with the substrate and includes a trench-defining wall, a semiconductor layer, and a semiconductor material. The trench-defining wall defines a trench. The semiconductor layer is formed over the trench-defining wall, partially fills the trench, substantially covers the trench-defining wall, and includes germanium. The semiconductor material is formed over the semiconductor layer and includes germanium, a percentage composition of which is greater than a percentage composition of the germanium of the semiconductor layer. The S/D contact is formed over the S/D junction. | |||
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5 | US2021020524A1 |
Hybrid Source Drain Regions Formed Based on Same Fin and Methods Forming Same
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Publication/Patent Number: US2021020524A1 | Publication Date: 2021-01-21 | Application Number: 16/515,484 | Filing Date: 2019-07-18 | Inventor： Wang, Pei-hsun Chen, Shih-cheng Lin, Chun-hsiung Wang, Chih-hao | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L21/8238 | Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin. | |||
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6 | US2021035890A1 |
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
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Publication/Patent Number: US2021035890A1 | Publication Date: 2021-02-04 | Application Number: 17/074,652 | Filing Date: 2020-10-20 | Inventor： Yu, Chen-hua Yu, Chun-hui Yee, Kuo-chung | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L23/495 | Abstract: A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads. | |||
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7 | US2021035861A1 |
Barrier-Free Approach For Forming Contact Plugs
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Publication/Patent Number: US2021035861A1 | Publication Date: 2021-02-04 | Application Number: 16/527,389 | Filing Date: 2019-07-31 | Inventor： Chen, Ching-yi Lin, Sheng-hsuan Loh, Wei-yip Chen, Hung-hsu Chang, Chih-wei | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L21/768 | Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer. | |||
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8 | US2021036097A1 |
INTERCONNECT LAYOUT FOR SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2021036097A1 | Publication Date: 2021-02-04 | Application Number: 16/738,095 | Filing Date: 2020-01-09 | Inventor： Tsai, Chun-hsiung More, Shahaji B. Lin, Yu-ming Wann, Clement Hsingjen | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L49/02 | Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via. | |||
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9 | US10916656B2 |
MOS devices having epitaxy regions with reduced facets
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Publication/Patent Number: US10916656B2 | Publication Date: 2021-02-09 | Application Number: 16/937,359 | Filing Date: 2020-07-23 | Inventor： Sung, Hsueh-chang Li, Kun-mu Lee, Tze-liang Li, Chii-horng Kwok, Tsz-mei | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L29/78 | Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. | |||
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10 | US2021043625A1 |
METHOD OF FABRICATING SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2021043625A1 | Publication Date: 2021-02-11 | Application Number: 17/069,876 | Filing Date: 2020-10-14 | Inventor： Chang, Che-cheng Lin, Chih-han Tseng, Horng-huei | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L27/088 | Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack. | |||
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11 | US2021043499A1 |
INSULATING CAP ON CONTACT STRUCTURE AND METHOD FOR FORMING THE SAME
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Publication/Patent Number: US2021043499A1 | Publication Date: 2021-02-11 | Application Number: 17/078,606 | Filing Date: 2020-10-23 | Inventor： Tsai, Kuo-chiang Su, Fu-hsiang Yu, Ke-jing Chen, Jyh-huei | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L21/768 | Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate electrode layer formed over a substrate, and a gate spacer adjacent to the gate electrode layer. The semiconductor device structure includes a source/drain contact structure formed over the substrate and adjacent to the gate electrode layer. An air gap is formed between the gate spacer and the source/drain contact structure, and the air gap is in direct contact with the gate spacer. | |||
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12 | US2021043239A1 |
MEMORY CIRCUIT AND METHOD OF OPERATING SAME
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Publication/Patent Number: US2021043239A1 | Publication Date: 2021-02-11 | Application Number: 17/076,965 | Filing Date: 2020-10-22 | Inventor： Tsai, Jui-che Lee, Cheng Hung Lu, Shih-lien Linus | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: G11C7/22 | Abstract: A memory circuit includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier is coupled to the first memory cell by a first bit line, and coupled to the second memory cell by a second bit line. The sense amplifier includes a header switch, a footer switch, a first cross-coupled inverter and a second cross-coupled inverter. The header switch has a first size, and is coupled to a first node and a first supply voltage. The footer switch has a second size, and is coupled to a second node and a second supply voltage. The first size is greater than the second size. The first size includes a first number of fins or a first channel width. The second size includes a second number of fins or a second channel width. | |||
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13 | US10930547B2 |
Semiconductor structure and manufacturing method thereof
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Publication/Patent Number: US10930547B2 | Publication Date: 2021-02-23 | Application Number: 16/046,495 | Filing Date: 2018-07-26 | Inventor： Tsai, Min-ying Tu, Yeur-luen | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L27/32 | Abstract: The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the III-V etch to stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer. | |||
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14 | US10930628B2 |
Photonic semiconductor device and method
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Publication/Patent Number: US10930628B2 | Publication Date: 2021-02-23 | Application Number: 16/437,151 | Filing Date: 2019-06-11 | Inventor： Chang, Chih-chieh Tsai, Chung-hao Wang, Chuei-tang Hsia, Hsing-kuo Yu, Chen-hua | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L25/16 | Abstract: A method includes forming multiple photonic devices in a semiconductor wafer, forming a v-shaped groove in a first side of the semiconductor wafer, forming an opening extending through the semiconductor wafer, forming multiple conductive features within the opening, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the v-shaped groove, depositing a molding material within the opening, wherein the multiple conductive features are separated by the molding material, after depositing the molding material, removing the polymer material to expose the v-shaped groove, and placing an optical fiber within the v-shaped groove. | |||
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15 | US2021057525A1 |
GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICE
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Publication/Patent Number: US2021057525A1 | Publication Date: 2021-02-25 | Application Number: 16/550,049 | Filing Date: 2019-08-23 | Inventor： Chiang, Kuo-cheng Su, Huan-chieh Ju, Shi Ning Pan, Kuan-ting Wang, Chih-hao | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L29/06 | Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires. | |||
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16 | US2021057276A1 |
Melting Laser Anneal Of Epitaxy Regions
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Publication/Patent Number: US2021057276A1 | Publication Date: 2021-02-25 | Application Number: 16/549,213 | Filing Date: 2019-08-23 | Inventor： Liu, Su-hao Chen, Wen-yen Chen, Tz-shian Sung, Cheng-jung Wang, Li-ting Chen, Liang-yin Chang, Huicheng Yeo, Yee-chia Jang, Syun-ming | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L21/768 | Abstract: A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten. | |||
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17 | US2021057216A1 |
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
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Publication/Patent Number: US2021057216A1 | Publication Date: 2021-02-25 | Application Number: 16/549,502 | Filing Date: 2019-08-23 | Inventor： Peng, Chun-yen Lai, Te-yang Yeong, Sai-hooi Chui, Chi On | Assignee: Taiwan semiconductor manufacturing company ltd | IPC: H01L21/02 | Abstract: A method for forming a crystalline high-k dielectric layer and controlling the crystalline phase and orientation of the crystal growth of the high-k dielectric layer during an anneal process. The crystalline phase and orientation of the crystal growth of the dielectric layer may be controlled using seeding sections of the dielectric layer serving as nucleation sites and using a capping layer mask during the anneal process. The location of the nucleation sites and the arrangement of the capping layer allow the orientation and phase of the crystal growth of the dielectric layer to be controlled during the anneal process. Based on the dopants and the process controls used the phase can be modified to increase the permittivity and/or the ferroelectric property of the dielectric layer. |
