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1
US2021005513A1
METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2021005513A1 Publication Date: 2021-01-07 Application Number: 16/626,772 Filing Date: 2019-11-19 Inventor: Song, Baoying   Xie, Yan   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L21/768 Abstract: A method of fabricating a semiconductor device, including: providing a front-end component including a substrate, a dielectric layer on a front side of the substrate, a metal layer embedded in the dielectric layer, a hole and an isolation layer; forming a polymer layer which covers a surface of the isolation layer; removing a portion of the polymer layer and at least a partial thickness of a portion of the isolation layer over the bottom of the hole by etching both the polymer layer and the isolation layer; removing the polymer layer; and successively repeating steps of forming a polymer layer, etching both the polymer layer and the isolation layer and removing the polymer layer, until the metal layer is exposed. This method ensures that the metal layer is exposed without loss of the isolation layer over a side wall of the hole and a top surface of the front-end component.
2
US2020075460A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020075460A1 Publication Date: 2020-03-05 Application Number: 16/397,066 Filing Date: 2019-04-29 Inventor: Hu, Xing   Zhou, Yu   Liu, Tianjian   Hu, Sheng   Zhao, Changlin   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L23/48 Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In the device, the isolation layer is used to prevent the first metal layer and the second metal layer which are over-etched and back-splashed from diffusing to a first substrate; and the isolation layer serves as a barrier layer to prevent an interconnection layer from diffusing into the first substrate. Further, the isolation layer includes a silicon nitride layer, which is advantageous for preventing the metal layers from back-splashing and diffusing to the sidewall of the first substrate. The isolation layer further includes a first silicon oxide layer and a second silicon oxide layer, wherein the second silicon oxide layer is used to protect the silicon nitride layer from being etched and consumed and the first silicon oxide layer is used to improve the adhesion between the silicon nitride layer and the first substrate.
3
US10732662B2
Band-gap reference circuit
Publication/Patent Number: US10732662B2 Publication Date: 2020-08-04 Application Number: 16/212,080 Filing Date: 2018-12-06 Inventor: Tang, Yuan   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: G05F3/26 Abstract: A band-gap reference circuit including a charge pump circuit and a reference circuit is disclosed. The charge pump circuit is powered by a supply voltage and thereby outputs a regulating voltage which is higher than the supply voltage and powers the reference circuit such that the reference circuit outputs a band-gap reference voltage. Powering the reference circuit with the regulating voltage that is made higher than the supply voltage by the charge pump circuit enables 1) normal operation of the band-gap reference circuit at the supply voltage that is lower than a lowest voltage required by the band-gap reference circuit; and 2) minimization (almost elimination) of fluctuations in the regulating voltage output from the charge pump circuit and hence a stable and more accurate band-gap reference voltage output from the band-gap reference circuit.
4
US10650866B2
Charge pump drive circuit
Publication/Patent Number: US10650866B2 Publication Date: 2020-05-12 Application Number: 16/194,761 Filing Date: 2018-11-19 Inventor: Tang, Yuan   Sheng, Bin   Zhang, Shengbo   Luo, Yi   Hsu, Jen-tai   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: G11C5/14 Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit includes a first pulse generating circuit and a second pulse generating circuit. Each of the first pulse generating circuit and the second pulse generating circuit is configured to connect to a charge pump. The first pulse generating circuit is configured to provide the charge pump with a series of first pulse signals. The second pulse generating circuit is configured to generate a second pulse signal in response to and based on an address translation detection signal and provide the second pulse signal to the charge pump or to the first pulse generating circuit. The first pulse generating circuit generates an additional first pulse signals based on the second pulse signal.
5
US2020075550A1
MULTI-WAFER BONDING STRUCTURE AND BONDING METHOD
Publication/Patent Number: US2020075550A1 Publication Date: 2020-03-05 Application Number: 16/249,118 Filing Date: 2019-01-16 Inventor: Ye, Guoliang   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L25/065 Abstract: A multi-wafer bonding structure and bonding method are disclosed. The multi-wafer bonding structure includes a first unit and a second unit, a metal layer of each wafer in the first unit electrically connected to an interconnection layer of the first unit, a first bonding layer in the first unit electrically connected to the interconnection layer of the first unit, a second bonding layer in the second unit electrically connected to a metal layer of the second unit, and the first bonding layer being in contact with the second bonding layer to achieve an electrical connection, thereby achieving the electrical connection among the interconnection layer of the first unit, the first bonding layer, the second bonding layer and the metal layer of each wafer.
6
US2020075482A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020075482A1 Publication Date: 2020-03-05 Application Number: 16/393,223 Filing Date: 2019-04-24 Inventor: Ye, Guoliang   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L23/522 Abstract: A semiconductor device and a manufacturing method thereof are disclosed. Two etching processes are used to form openings above a first wafer metal layer and a second wafer metal layer respectively in different regions, a substrate on the upper first wafer is exposed at the two openings, the exposed portion is etched such that the sidewall of the substrate at the exposed portion is etched inward, and an interconnection layer is formed to be respectively electrically connected to the metal layers of the two wafers, thereby realizing the metal interconnection of the two wafers. The device adopts etching to recess the exposed substrate of the first wafer inward, to effectively prevent the isolation layer from being damaged during the subsequent dry etching process and ensure that the isolation layer has a function of isolating the interconnection layer in the subsequent process, thereby improving the yield and performance of the device.
7
US10770153B2
Charge pump drive circuit with two switch signals
Publication/Patent Number: US10770153B2 Publication Date: 2020-09-08 Application Number: 16/226,094 Filing Date: 2018-12-19 Inventor: Tang, Yuan   Mao, Zhifeng   Xu, Yi   Chang, Hung-yu   Hsu, Jen-tai   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: G11C16/30 Abstract: A charge pump drive circuit is disclosed. The charge pump drive circuit provides a switch signal to a charge pump which provides a memory with a read voltage and a read current. The charge pump drive circuit includes a read drive circuit and a standby drive circuit. The read drive circuit is powered by a first power supply and provides the charge pump with a switch signal when the memory is in an active reading state. The standby drive circuit is powered by a second power supply and provides the charge pump with a switch signal when the memory is in a read standby state. The first power supply provides a voltage level ranging from 1.6 V to 3.8 V, and the second power supply provides a voltage level of 1.5 V.
8
US10714200B2
Method for programming electrically programmable fuse
Publication/Patent Number: US10714200B2 Publication Date: 2020-07-14 Application Number: 16/200,146 Filing Date: 2018-11-26 Inventor: Yu, Kuilong   Han, Kun   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: G11C17/18 Abstract: A method for programming an electrically programmable fuse is disclosed. As conductive medium of the electrically programmable fuse exhibits different physical changes under different conditions, the conductive medium is changed from an initial physical state to a first physical state by using a first programming condition to program the electrically programmable fuse from a low resistance state to a medium resistance state, and the conductive medium is changed from the initial physical state or the first physical state to a second physical state by using a second programming condition to program the electrically programmable fuse from the low resistance state or the medium resistance state to a high resistance state. Transitions of three information storage states are achieved through two different programming conditions, so that the information storage density and chip area utilization rate of an electrically programmable fuse device can be significantly improved, and chip size reduction is facilitated.
9
US2020075483A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020075483A1 Publication Date: 2020-03-05 Application Number: 16/397,130 Filing Date: 2019-04-29 Inventor: Zhou, Yu   Liu, Tianjian   Hu, Sheng   Zhao, Changlin   Hu, Xing   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L23/522 Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a first opening and a second opening are vertically separated, and are no longer restricted by the condition that a deep upper opening needs to be filled with a thick photoresist when a TSV nested hole in vertical communication forms a middle opening and lower opening, thereby satisfying devices with different thicknesses requirements. The design is no longer restricted by the lateral process of the TSV nested hole, thereby enhancing the flexibility of the design. In the photolithography process, the deep hole does not need to be filled with the photoresist, the photoresist does not need to be thick, thereby reducing the complexity of the photolithography process and improving the exposure effect. The first metal layer and the second metal layer are directly led out via a first trench, thereby simplifying the process and reducing the production cost.
10
US2020075552A1
MULTI-WAFER STACK STRUCTURE AND FORMING METHOD THEREOF
Publication/Patent Number: US2020075552A1 Publication Date: 2020-03-05 Application Number: 16/393,179 Filing Date: 2019-04-24 Inventor: Zhao, Changlin   Liu, Tianjian   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L25/065 Abstract: A multi-wafer stack structure and fabricating method thereof are disclosed. In the multi-wafer stack structure, the first interconnection layer is electrically connected to the second metal layer and the first metal layer via the first opening, the second interconnection layer is electrically connected to the first interconnection layer via the second openings, the third interconnection layer is electrically connected to the third metal layer via the third openings, and the second interconnection layer is in contact with the third interconnection layer, so that there is no need to reserve the wire pressure welding space between the wafers and a silicon substrate is eliminated, the overall device thickness of the multi-wafer stack package is reduced. Moreover, the design processing of the silicon substrate and a plurality of common pads on the silicon substrate is eliminated, thereby reducing the parasitic capacitance and power loss, and increasing the transmission speed.
11
US2020075459A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020075459A1 Publication Date: 2020-03-05 Application Number: 16/392,988 Filing Date: 2019-04-24 Inventor: Zeng, Tian   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L23/48 Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.
12
US10867969B2
Multi-wafer stacking structure and fabrication method thereof
Publication/Patent Number: US10867969B2 Publication Date: 2020-12-15 Application Number: 16/880,103 Filing Date: 2020-05-21 Inventor: Zhao, Changlin   Zeng, Tian   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L21/76 Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
13
US10784152B2
Method of making an interconnection between wafers after wafer level stacking, based on 3D-IC technology
Publication/Patent Number: US10784152B2 Publication Date: 2020-09-22 Application Number: 16/397,157 Filing Date: 2019-04-29 Inventor: Liu, Heng   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L21/768 Abstract: A manufacturing method of a semiconductor device is disclosed, including: providing a first wafer and a second wafer that are bonded, a back surface of the first substrate of the first wafer is provided with a passivation layer; performing a photolithography and etching process to form a first opening; forming a hard mask layer, the hard mask layer covers at least a sidewall surface of the first opening; performing an etching process to form a second opening; performing a photolithography and etching process to form a third opening; and forming an interconnection layer. A back surface of a first substrate is provided with a passivation layer, after a first opening is formed, a hard mask layer is formed on a sidewall surface of the first opening, and a maskless etching process is performed to form a second opening, thereby simplifying the process, eliminating one photomask and reducing the production cost.
14
US2020075549A1
MULTI-WAFER STACKING STRUCTURE AND FABRICATION METHOD THEREOF
Publication/Patent Number: US2020075549A1 Publication Date: 2020-03-05 Application Number: 16/234,152 Filing Date: 2018-12-27 Inventor: Zhao, Changlin   Zeng, Tian   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L25/065 Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
15
US10811339B2
Semiconductor device and manufacturing method thereof
Publication/Patent Number: US10811339B2 Publication Date: 2020-10-20 Application Number: 16/392,988 Filing Date: 2019-04-24 Inventor: Zeng, Tian   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L23/48 Abstract: A semiconductor device and a manufacturing method thereof are disclosed. In which a uniform metal layer is formed above the second metal layer of the second wafer, the uniform metal layer is electrically connected to the second metal layer, and the uniform metal layer and the first metal layer are made of the same material. The uniform metal layer and the first metal layer simultaneously exposed by the subsequently formed TSV hole are made of the same material, the degree of over-etching is relatively easy to control in the etching process, and cross contamination of cleaning agents in the cleaning process can be avoided. In addition, when the interconnection layer is electrically connected to the first metal layer and the uniform metal layer, since the uniform metal layer and the first metal layer are made of the same material, the interconnection layer has better contact performance with the two.
16
US10684316B2
Voltage detection circuit for charge pump
Publication/Patent Number: US10684316B2 Publication Date: 2020-06-16 Application Number: 16/228,332 Filing Date: 2018-12-20 Inventor: Tang, Yuan   Alex, Wang Shiou-yu   Hsu, Jen-tai   Mao, Zhifeng   Chen, Sean   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H03K5/153 Abstract: A voltage detection circuit for a charge pump is disclosed. The voltage detection circuit includes a sampling circuit and a latch circuit. The sampling circuit is configured to sample a supply voltage and provide the latch circuit with a sampled voltage. The latch circuit is configured to detect the sampled voltage and latch a result of the detection. And the latch circuit is connected to a voltage regulation circuit which is configured to regulate a charge-pump cascade structure in the charge pump based on the result of the detection so as to maintain an output voltage of the charge pump stable.
17
US10700042B2
Multi-wafer stacking structure and fabrication method thereof
Publication/Patent Number: US10700042B2 Publication Date: 2020-06-30 Application Number: 16/234,152 Filing Date: 2018-12-27 Inventor: Zhao, Changlin   Zeng, Tian   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L21/76 Abstract: A multi-wafer stacking structure and fabrication method are disclosed. In the multi-wafer stacking structure, a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
18
US2020144108A1
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020144108A1 Publication Date: 2020-05-07 Application Number: 16/397,157 Filing Date: 2019-04-29 Inventor: Liu, Heng   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L21/768 Abstract: A manufacturing method of a semiconductor device is disclosed, including: providing a first wafer and a second wafer that are bonded, a back surface of the first substrate of the first wafer is provided with a passivation layer; performing a photolithography and etching process to form a first opening; forming a hard mask layer, the hard mask layer covers at least a sidewall surface of the first opening; performing an etching process to form a second opening; performing a photolithography and etching process to form a third opening; and forming an interconnection layer. A back surface of a first substrate is provided with a passivation layer, after a first opening is formed, a hard mask layer is formed on a sidewall surface of the first opening, and a maskless etching process is performed to form a second opening, thereby simplifying the process, eliminating one photomask and reducing the production cost.
19
US2020286861A1
MULTI-WAFER STACKING STRUCTURE AND FABRICATION METHOD THEREOF
Publication/Patent Number: US2020286861A1 Publication Date: 2020-09-10 Application Number: 16/880,103 Filing Date: 2020-05-21 Inventor: Zhao, Changlin   Zeng, Tian   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H01L25/065 Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.
20
US10879880B2
Oscillator
Publication/Patent Number: US10879880B2 Publication Date: 2020-12-29 Application Number: 16/210,904 Filing Date: 2018-12-05 Inventor: Tang, Yuan   Assignee: Wuhan xinxin semiconductor manufacturing co ltd   IPC: H03K3/03 Abstract: An oscillator including two sequentially connected pulse generation circuits is disclosed. Each pulse generation circuit includes a charge/discharge circuit and a switch circuit and outputs a first or second signal depending on an input signal. The switch circuit controls the charge/discharge circuit so that the latter is charged when the input signal is at a first level and discharged when the input signal is at a second level higher than the first level. When the input signal is at the first level, the first signal is at the first level and the second signal is at the second level. When the input signal is at the second level, the first signal is at the second level and the second signal is at the first level. Upon completion of discharge of the charge/discharge circuit, the first signal changes to the first level and the second signal changes to the second level.