Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1 EP2800097B1
STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHODS THEREFOR
Publication/Patent Number: EP2800097B1 Publication Date: 2018-03-21 Application Number: 12865338.3 Filing Date: 2012-12-20 Inventor: Adachi, Naohiro   Tsutsui, Keiichi   Nakanishi, Kenichi   Okubo, Hideaki   Yamamoto, Makiko   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G11C13/00 Abstract: Provided is a storage control device including a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data, a first write processing unit configured to rewrite the memory cell to the first value when write data is the first value and the first read data is the second value, a second read processing unit configured to read second read data based on a second threshold value different from the first threshold value in the memory cell, and a second write processing unit configured to rewrite the memory cell to the second value when the write data is the second value and the second read data is the first value. Provided is a storage control device including a first read processing unit configured to read data having any one value of a first value or a second value based on a first threshold value in a memory cell, the data being read as first read data, a first write processing unit ...More ...Less
2 US10120614B2
Storage device, storage system, and method of controlling storage device
Publication/Patent Number: US10120614B2 Publication Date: 2018-11-06 Application Number: 15/311,555 Filing Date: 2015-05-19 Inventor: Iwaki, Hiroyuki   Ishii, Ken   Ikegaya, Ryoji   Nakanishi, Kenichi   Fujinami, Yasushi   Adachi, Naohiro   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful. A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in ...More ...Less
3 US9792173B2
Interface control circuit, memory system, and method of controlling an interface control circuit
Publication/Patent Number: US9792173B2 Publication Date: 2017-10-17 Application Number: 14/271,732 Filing Date: 2014-05-07 Inventor: Adachi, Naohiro   Shibahara, Yoshiyuki   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/07 Abstract: Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error correction unit is configured to execute error correction processing of correcting the error when the error occurs. The adjustment control unit is configured to start adjustment processing of adjusting a transmission characteristic of the interface when the error occurs. Disclosed is an interface control circuit including an error detection unit, an error correction unit, and an adjustment control unit. The error detection unit is configured to detect whether an error occurs in error correction coded data transmitted via an interface. The error ...More ...Less
4 US9836392B2
Storage control apparatus to control pre-processing operations
Publication/Patent Number: US9836392B2 Publication Date: 2017-12-05 Application Number: 14/692,233 Filing Date: 2015-04-21 Inventor: Adachi, Naohiro   Tsutsui, Keiichi   Nakanishi, Kenichi   Okubo, Hideaki   Fujinami, Yasushi   Ishii, Ken   Assignee: SONY CORPORATION   IPC: G06F12/00 Abstract: A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to serve as a write-operation object; and a pre-read processing block for reading out pre-read data from the data area prior to the write operation if a result of the determination indicates that the pre-processing is to be executed. The apparatus further includes a bit operating block for carrying out: the pre-processing and one of the erase and program operations which is not the pre-processing as post-processing if a result of the determination indicates that the pre-processing is to be executed; and the post-processing without carrying out the pre-processing if a determination result indicates that the pre-processing is not to be executed. A storage control apparatus includes: a pre-processing-execution determining block for determining whether or not either one of an erase operation and a program operation is to be executed as pre-processing in a write operation to be carried out on a predetermined data area to ...More ...Less
5 US2017109099A1
STORAGE DEVICE, STORAGE SYSTEM, AND METHOD OF CONTROLLING STORAGE DEVICE
Publication/Patent Number: US2017109099A1 Publication Date: 2017-04-20 Application Number: 15/311,555 Filing Date: 2015-05-19 Inventor: Iwaki, Hiroyuki   Ishii, Ken   Ikegaya, Ryoji   Nakanishi, Kenichi   Fujinami, Yasushi   Adachi, Naohiro   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in the write address, and generates an address different from the write address in which the writing is performed as an alternative write address and writes the data in the alternative write address when the writing of the data is unsuccessful. A storage device writes data at a high speed. The storage device is provided with a data area and a control unit. In the data area, a write position is specified by a write address. Also, the control unit writes the data in the write address when instructed to write the data in ...More ...Less
6 US9852812B2
Storage apparatus
Publication/Patent Number: US9852812B2 Publication Date: 2017-12-26 Application Number: 20/141,453 Filing Date: 2014-11-06 Inventor: Nakanishi, Kenichi   Fujinami, Yasushi   Iwaki, Hiroyuki   Ikegaya, Ryoji   Ishii, Ken   Adachi, Naohiro   Assignee: Sony Corporation   IPC: G11C7/00 Abstract: There is provided a storage apparatus that includes an address obtaining section
7 US2017185478A1
MEMORY CONTROLLER, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: US2017185478A1 Publication Date: 2017-06-29 Application Number: 15/325,191 Filing Date: 2015-06-23 Inventor: Sakai, Lui   Tsutsui, Keiichi   Fujinami, Yasushi   Iwaki, Hiroyuki   Ishii, Ken   Adachi, Naohiro   Ikegaya, Ryoji   Nakanishi, Kenichi   Assignee: SONY CORPORATION   IPC: G06F11/10 Abstract: The convenience of an information processing system is improved. In a memory controller of the information processing system, a request generation unit generates, with respect to a nonvolatile memory including a data area in which data is stored and a redundancy area in which a redundancy for performing error detection and error correction of the data is stored, a request of requesting writing or reading for any one of the data, and the redundancy, a code word constituted of the data and the redundancy. A control unit issues the generated request and controls writing and reading with respect to the nonvolatile memory. The convenience of an information processing system is improved. In a memory controller of the information processing system, a request generation unit generates, with respect to a nonvolatile memory including a data area in which data is stored and a redundancy area in which a ...More ...Less
8 WO2016056290A1
MEMORY CONTROLLER
Publication/Patent Number: WO2016056290A1 Publication Date: 2016-04-14 Application Number: 2015070798 Filing Date: 2015-07-22 Inventor: Fujinami, Yasushi   Adachi, Naohiro   Assignee: Sony Corporation   IPC: G06F12/02 Abstract: A substitution process is performed on a page unit basis without an increase in memory management information. A block management table stores a physical block address of a storage device that manages a memory region for each block comprising a plurality of pages
9 US9483425B2
Memory including a band width conversion unit, memory system and memory control method using the same
Publication/Patent Number: US9483425B2 Publication Date: 2016-11-01 Application Number: 14/459,966 Filing Date: 2014-08-14 Inventor: Terada, Haruhiko   Sakai, Lui   Adachi, Naohiro   Assignee: Sony Corporation   IPC: G06F13/12 Abstract: A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus. A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for ...More ...Less
10 US9361952B2
Storage controlling apparatus, memory system, information processing system and storage controlling method
Publication/Patent Number: US9361952B2 Publication Date: 2016-06-07 Application Number: 13/780,655 Filing Date: 2013-02-28 Inventor: Nakanishi, Kenichi   Tsutsui, Keiichi   Fujinami, Yasushi   Adachi, Naohiro   Okubo, Hideaki   Ishii, Ken   Shinbashi, Tatsuo   Assignee: SONY CORPORATION   IPC: G11C7/00 Abstract: Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes rewriting to one of the binary values and rewriting to the other one of the binary values in order in a writing process, to generate decision data indicative of a result of the decision; and a write side outputting portion configured to output, when it is decided that the bit number is greater than the reference value, the input data at least part of which is inverted as write data to the memory cell together with the decision data. Disclosed herein is a storage controlling apparatus including: a decision portion configured to decide whether or not a bit number of a specific value from between binary values is greater than a reference value in at least part of input data to a memory cell, which executes ...More ...Less