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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
EP2665096B1
A METHOD OF WAFER-SCALE INTEGRATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP2665096B1 Publication Date: 2020-04-22 Application Number: 12168069.8 Filing Date: 2012-05-15 Inventor: Cassidy, Cathal   Siegert, Jörg   Schrank, Franz   Assignee: ams AG   IPC: H01L27/146
2
US10828622B2
Engineering high-performance palladium core magnesium oxide porous shell nanocatalysts via heterogeneous gas-phase synthesis
Publication/Patent Number: US10828622B2 Publication Date: 2020-11-10 Application Number: 15/736,721 Filing Date: 2016-06-28 Inventor: Sowwan, Mukhles Ibrahim   Cassidy, Cathal   Singh, Vidya Dhar   Assignee: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATION   IPC: B01J37/34 Abstract: A novel catalyst includes a plurality of nanoparticles, each nanoparticle including a core made of a catalytic metal and a porous shell surrounding the core, made of metal oxide, the porous shell preserving a catalytic function of the core and reducing reduction of the core and coalescence of the nanoparticles.
3
US10332931B2
Semiconductor device for wafer-scale integration
Publication/Patent Number: US10332931B2 Publication Date: 2019-06-25 Application Number: 15/455,055 Filing Date: 2017-03-09 Inventor: Cassidy, Cathal   Siegert, Joerg   Schrank, Franz   Assignee: ams AG   IPC: H01L27/146 Abstract: The semiconductor device comprises a semiconductor wafer with an integrated circuit, formed by a plurality of dies, a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material, the semiconductor wafer and the further semiconductor wafer being bonded to one another by means of a bonding layer, and an electrically conductive contact layer arranged on the further semiconductor wafer opposite to the bonding layer.
4
EP2620978B1
Semiconductor device with internal substrate contact and method of production
Publication/Patent Number: EP2620978B1 Publication Date: 2019-07-24 Application Number: 12152485.4 Filing Date: 2012-01-25 Inventor: Kraft, Jochen   Teva, Jordi   Cassidy, Cathal   Koppitsch, Günther   Assignee: austriamicrosystems AG   IPC: H01L21/74
5
EP2584598B1
Method of producing a semiconductor device comprising a through-substrate via and a capping layer and corresponding semiconductor device
Publication/Patent Number: EP2584598B1 Publication Date: 2018-12-05 Application Number: 11185999.7 Filing Date: 2011-10-20 Inventor: Schrank, Franz   Cassidy, Cathal   Assignee: ams AG   IPC: H01L21/768 Abstract: The method of producing a semiconductor device comprises the steps of providing a semiconductor substrate (1) with an electrically conductive structure (11), forming a hole (4) through the substrate in a direction normal to its main surface (10), and forming a through-substrate via (5) in the hole by introducing an electrically conductive material without filling the hole. A capping layer (6) is applied above the main surface in such a way that the capping layer closes the remaining inner volume (14) of the through-substrate via without filling the hole or at least partially covers an annular cavity surrounding the through-substrate via. The capping layer is structured, so that the electrically conductive structure is not completely covered by the capping layer.
6
EP3313567A1
ENGINEERING HIGH-PERFORMANCE PALLADIUM CORE MAGNESIUM OXIDE POROUS SHELL NANOCATALYSTS VIA HETEROGENEOUS GAS-PHASE SYNTHESIS
Publication/Patent Number: EP3313567A1 Publication Date: 2018-05-02 Application Number: 16817467.0 Filing Date: 2016-06-28 Inventor: Sowwan, Mukhles Ibrahim   Cassidy, Cathal   Singh, Vidya Dhar   Assignee: Okinawa Institute of Science and Technology School Corporation   IPC: B01J23/44
7
US2018193820A1
ENGINEERING HIGH-PERFORMANCE PALLADIUM CORE MAGNESIUM OXIDE POROUS SHELL NANOCATALYSTS VIA HETEROGENEOUS GAS-PHASE SYNTHESIS
Publication/Patent Number: US2018193820A1 Publication Date: 2018-07-12 Application Number: 15/736,721 Filing Date: 2016-06-28 Inventor: Singh, Vidya Dhar   Cassidy, Cathal   Sowwan, Mukhles Ibrahim   Assignee: Okinawa Institute of Science and Technology School Corporation   IPC: B01J37/14 Abstract: A novel catalyst includes a plurality of nanoparticles, each nanoparticle including a core made of a catalytic metal and a porous shell surrounding the core, made of metal oxide, the porous shell preserving a catalytic function of the core and reducing reduction of the core and coalescence of the nanoparticles.
8
US201890393A1
Method and arrangement for analyzing a semiconductor element and method for manufacturing a semiconductor component
Publication/Patent Number: US201890393A1 Publication Date: 2018-03-29 Application Number: 20/171,582 Filing Date: 2017-11-29 Inventor: Cassidy, Cathal   Schrems, Martin   Gehles, Helene   Assignee: ams AG   IPC: H01L21/02 Abstract: According to the improved concept, a method for analyzing a semiconductor element comprising polymer residues located on a surface of the semiconductor element is provided. The method comprises marking at least a fraction of the residues by exposing the semiconductor element to a fluorescent substance and detecting the marked residues by visualizing the marked residues on the surface of the semiconductor element using fluorescence microscopy.
9
US2017179183A1
SEMICONDUCTOR DEVICE FOR WAFER-SCALE INTEGRATION
Publication/Patent Number: US2017179183A1 Publication Date: 2017-06-22 Application Number: 15/455,055 Filing Date: 2017-03-09 Inventor: Cassidy, Cathal   Siegert, Joerg   Schrank, Franz   Assignee: ams AG   IPC: H01L27/146 Abstract: The semiconductor device comprises a semiconductor wafer with an integrated circuit, formed by a plurality of dies, a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material, the semiconductor wafer and the further semiconductor wafer being bonded to one another by means of a bonding layer, and an electrically conductive contact layer arranged on the further semiconductor wafer opposite to the bonding layer.
10
WO2017002357A1
ENGINEERING HIGH-PERFORMANCE PALLADIUM CORE MAGNESIUM OXIDE POROUS SHELL NANOCATALYSTS VIA HETEROGENEOUS GAS-PHASE SYNTHESIS
Publication/Patent Number: WO2017002357A1 Publication Date: 2017-01-05 Application Number: 2016003093 Filing Date: 2016-06-28 Inventor: Singh, Vidya Dhar   Cassidy, Cathal   Sowwan, Mukhles Ibrahim   Assignee: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATION   IPC: B01J23/44 Abstract: A novel catalyst includes a plurality of nanoparticles
11
US9735101B2
Semiconductor device with through-substrate via covered by a solder ball
Publication/Patent Number: US9735101B2 Publication Date: 2017-08-15 Application Number: 15/283,183 Filing Date: 2016-09-30 Inventor: Cassidy, Cathal   Schrems, Martin   Schrank, Franz   Assignee: AMS AG   IPC: H01L23/48 Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises an annular cavity (18) and a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme.
12
US9633842B2
Metal induced nanocrystallization of amorphous semiconductor quantum dots
Publication/Patent Number: US9633842B2 Publication Date: 2017-04-25 Application Number: 14/774,226 Filing Date: 2014-03-07 Inventor: Singh, Vidya Dhar   Cassidy, Cathal   Sowwan, Mukhles Ibrahim   Assignee: OKINAWA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL CORPORATION   IPC: H01L21/02 Abstract: A method of forming crystallized semiconductor particles includes: forming amorphous semiconductor particles in a vacuumed aggregation chamber; transporting the amorphous semiconductor particles formed in the vacuumed aggregation chamber to a vacuumed deposition chamber within which a substrate is held; and applying a vapor of a metal catalyst to the amorphous semi-conductor particles while still in transit to the substrate in the vacuumed deposition chamber to induce crystallization of at least portion of the amorphous semiconductor particles via the metal catalyst in the transit, thereby depositing the crystallized semiconductor particles with the metal catalyst attached thereto onto the substrate.
13
US9852955B2
Method and arrangement for analyzing a semiconductor element and method for manufacturing a semiconductor component
Publication/Patent Number: US9852955B2 Publication Date: 2017-12-26 Application Number: 20/161,534 Filing Date: 2016-11-03 Inventor: Cassidy, Cathal   Schrems, Martin   Gehles, Helene   Assignee: ams AG   IPC: G01N21/64 Abstract: According to the improved concept
14
EP2973660B1
METAL INDUCED NANOCRYSTALLIZATION OF AMORPHOUS SEMICONDUCTOR QUANTUM DOTS
Publication/Patent Number: EP2973660B1 Publication Date: 2017-11-01 Application Number: 14762623.8 Filing Date: 2014-03-07 Inventor: Cassidy, Cathal   Sowwan, Mukhles Ibrahim   Singh, Vidya Dhar   Assignee: Okinawa Institute of Science and Technology School Corporation   IPC: C30B1/02
15
US2017365551A1
METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL
Publication/Patent Number: US2017365551A1 Publication Date: 2017-12-21 Application Number: 15/691,654 Filing Date: 2017-08-30 Inventor: Cassidy, Cathal   Schrems, Martin   Schrank, Franz   Assignee: ams AG   IPC: H01L23/522 Abstract: A semiconductor substrate is provided with an annular cavity extending from a front side of the substrate to an opposite rear side. A metallization is applied in the annular cavity, thereby forming a through-substrate via and leaving an opening of the annular cavity at the front side. A solder ball is placed above the opening and a reflow of the solder ball is effected, thereby forming a void of the through-substrate via, the void being covered by the solder ball.
16
US9773729B2
Method of producing a semiconductor device with through-substrate via covered by a solder ball
Publication/Patent Number: US9773729B2 Publication Date: 2017-09-26 Application Number: 15/283,189 Filing Date: 2016-09-30 Inventor: Cassidy, Cathal   Schrems, Martin   Schrank, Franz   Assignee: ams AG   IPC: H01L21/44 Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.
17
US9553039B2
Semiconductor device with through-substrate via covered by a solder ball and related method of production
Publication/Patent Number: US9553039B2 Publication Date: 2017-01-24 Application Number: 14/359,568 Filing Date: 2012-11-07 Inventor: Cassidy, Cathal   Schrems, Martin   Schrank, Franz   Assignee: AMS AG   IPC: H01L23/48 Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.
18
US9608035B2
Method of wafer-scale integration of semiconductor devices and semiconductor device
Publication/Patent Number: US9608035B2 Publication Date: 2017-03-28 Application Number: 14/401,499 Filing Date: 2013-04-05 Inventor: Cassidy, Cathal   Siegert, Joerg   Schrank, Franz   Assignee: AMS AG   IPC: H01L27/146 Abstract: The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (3), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer (6) arranged on the further semiconductor wafer (2) and a metal layer connecting the contact layer with an integrated circuit.
19
US2017018518A1
METHOD OF PRODUCING A SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL
Publication/Patent Number: US2017018518A1 Publication Date: 2017-01-19 Application Number: 15/283,189 Filing Date: 2016-09-30 Inventor: Cassidy, Cathal   Schrems, Martin   Schrank, Franz   Assignee: ams AG   IPC: H01L23/00 Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.
20
US2017025351A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL
Publication/Patent Number: US2017025351A1 Publication Date: 2017-01-26 Application Number: 15/283,183 Filing Date: 2016-09-30 Inventor: Cassidy, Cathal   Schrems, Martin   Schrank, Franz   Assignee: ams AG   IPC: H01L23/522 Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises an annular cavity (18) and a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three-dimensional integration is offered by this scheme.
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