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1
US10950603B2
Semiconductor device and method
Publication/Patent Number: US10950603B2 Publication Date: 2021-03-16 Application Number: 16/697,839 Filing Date: 2019-11-27 Inventor: Chang shih chieh   Lee, Cheng-han   Huang, Yi-min   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/088 Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.
2
US10937910B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Publication/Patent Number: US10937910B2 Publication Date: 2021-03-02 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Lin, Yu-ting   Pai, Yueh-ching   Chang shih chieh   Yang, Huai-tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
3
US2021050433A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN STRUCTURE HAVING MODIFIED SHAPE
Publication/Patent Number: US2021050433A1 Publication Date: 2021-02-18 Application Number: 17/089,138 Filing Date: 2020-11-04 Inventor: More, Shahaji B.   Chang shih chieh   Lee, Cheng-han   Yang, Huai-tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: H01L29/66 Abstract: Semiconductor structures and method for forming the same are provide. The semiconductor structure includes a fin structure protruding from a substrate and a gate structure formed across the fin structure. The semiconductor structure further includes an Arsenic-doped region formed in the fin structure and a source/drain structure formed over the Arsenic-doped region. In addition, a bottommost portion of the Arsenic-doped region is lower than a bottommost portion of the source/drain structure.
4
US2021004678A1
NEURAL CIRCUIT
Publication/Patent Number: US2021004678A1 Publication Date: 2021-01-07 Application Number: 16/846,427 Filing Date: 2020-04-13 Inventor: Chang shih chieh   Li, Sih-han   Sheu, Shyh-shyuan   Su, Jian-wei   Lee, Heng-yuan   Assignee: Industrial Technology Research Institute   IPC: G06N3/08 Abstract: A neural circuit is provided. The neural circuit includes a neural array. The neural array includes a plurality of semiconductor components. Each of the semiconductor components stores a weighting value to generate a corresponding output current or a corresponding equivalent resistance. The neural array receives a plurality of input signals to control the semiconductor components in the neural array and respectively generates the output currents or changes the equivalent resistances. Since the semiconductor components are coupled to each other, output of the neural array may generate a summation current or a summation equivalent resistance related to the input signals and a weighting condition, so that a computing result exhibits high performance.
5
US10930781B2
P-type strained channel in a fin field effect transistor (FinFET) device
Publication/Patent Number: US10930781B2 Publication Date: 2021-02-23 Application Number: 16/710,156 Filing Date: 2019-12-11 Inventor: More, Shahaji B.   Yang, Huai-tei   Chang shih chieh   Kuan, Shu   Lee, Cheng-han   Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.   IPC: H01L29/78 Abstract: In certain embodiments, a semiconductor device includes a substrate having an n-doped well feature and an epitaxial silicon germanium fin formed over the n-doped well feature. The epitaxial silicon germanium fin has a lower part and an upper part. The lower part has a lower germanium content than the upper part. A channel is formed from the epitaxial silicon germanium fin. A gate is formed over the epitaxial silicon germanium fin. A doped source-drain is formed proximate the channel.
6
US10855197B2
Power supply system
Publication/Patent Number: US10855197B2 Publication Date: 2020-12-01 Application Number: 16/459,317 Filing Date: 2019-07-01 Inventor: Chang shih chieh   Assignee: DELTA ELECTRONICS, INC.   IPC: H02M7/04 Abstract: A power supply system includes a power supply assembly, an auxiliary power circuit and a control unit. The power supply assembly converts input power into a first DC power when the input power outputted from an input power source is normal. The auxiliary power circuit includes at least one energy storage unit for providing a second DC power and power converter electrically connected between the energy storage unit and the load for converting the second DC power into an individual auxiliary power. The control unit drives the auxiliary power circuit to provide an overall auxiliary power to the load when the input power is normal and a transient power required by the load is greater than a upper limit rated value of an output power outputted from the power supply assembly, so as to compensate a difference value between the transient power and the upper limit rated value.
7
US2020220475A1
POWER SUPPLY SYSTEM
Publication/Patent Number: US2020220475A1 Publication Date: 2020-07-09 Application Number: 16/459,317 Filing Date: 2019-07-01 Inventor: Chang shih chieh   Assignee: DELTA ELECTRONICS, INC.   IPC: H02M7/04 Abstract: A power supply system includes a power supply assembly, an auxiliary power circuit and a control unit. The power supply assembly converts input power into a first DC power when the input power outputted from an input power source is normal. The auxiliary power circuit includes at least one energy storage unit for providing a second DC power and power converter electrically connected between the energy storage unit and the load for converting the second DC power into an individual auxiliary power. The control unit drives the auxiliary power circuit to provide an overall auxiliary power to the load when the input power is normal and a transient power required by the load is greater than a upper limit rated value of an output power outputted from the power supply assembly, so as to compensate a difference value between the transient power and the upper limit rated value.
8
US2020220379A1
POWER SUPPLY SYSTEM
Publication/Patent Number: US2020220379A1 Publication Date: 2020-07-09 Application Number: 16/503,965 Filing Date: 2019-07-05 Inventor: Chang shih chieh   Assignee: DELTA ELECTRONICS, INC.   IPC: H02J9/06 Abstract: A power supply system is connected to a load, and the power supply system includes a power supply apparatus and a backup apparatus. When an input power is normal, the power supply apparatus converts the input power into a first output power, provides the first output power to the power bus, and selectively provides the first output power to charge the backup apparatus, in which the first output power has a first rated upper-limit value. When the input power is normal and a required power of the load is greater than the first rated upper-limit value, the backup apparatus provides a second output power to the power bus so that the sum of the first output power and the second output power meets the required power of the load.
9
EP3616633A1
SURGICAL ACCESS SLEEVE AND SURGICAL ACCESS DEVICE COMPRISING THE SAME
Publication/Patent Number: EP3616633A1 Publication Date: 2020-03-04 Application Number: 19193447.0 Filing Date: 2019-08-23 Inventor: Ku, Kun-tai   Chang shih chieh   Assignee: Hwealthy Co., LTD.   IPC: A61B17/34 Abstract: A surgical access sleeve comprises a trocar sleeve (20). The trocar sleeve (20) includes: a trocar housing (22) including a housing base (22a) and a housing cover (22b) disposed on the housing base (22a), the housing base (22a) including an annular wall (221), a lower chamber (222) disposed inside the annular wall (221) and a first guide channel (2211) obliquely penetrating through the annular wall (221) but being not communicated with the lower chamber (222); and a trocar cannula (21) including a first open end (21a) connected with the trocar housing (22), a second open end (21b) located opposite to the first open end (21a), and a tube wall (23) disposed between the first open end (21a) and the second open end (21b), the tube wall (23) including a first upper guide through hole (23a) and a first lower guide through hole (23b), wherein the first guide channel (2211), the first upper guide through hole (23a), and the first lower guide through hole (23b) are coaxially disposed along a virtual axis (25).
10
US2020135476A1
FinFET Device and Method of Forming
Publication/Patent Number: US2020135476A1 Publication Date: 2020-04-30 Application Number: 16/728,918 Filing Date: 2019-12-27 Inventor: Huang, Yi-min   Yang, Huai-tei   Chang shih chieh   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/285 Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
11
US2020105936A1
FINFET DEVICE AND METHOD OF FORMING SAME
Publication/Patent Number: US2020105936A1 Publication Date: 2020-04-02 Application Number: 16/245,519 Filing Date: 2019-01-11 Inventor: More, Shahaji B.   Chang shih chieh   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.
12
US2020098645A1
FinFET EPI Channels Having Different Heights on a Stepped Substrate
Publication/Patent Number: US2020098645A1 Publication Date: 2020-03-26 Application Number: 16/696,327 Filing Date: 2019-11-26 Inventor: Lee, Cheng-han   Ma, Chih-yu   Chang shih chieh   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/8238 Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.
13
EP3733987A1
OIL-WATER SEPARATOR WITH OIL DISCHARGE OUTLET ADJUSTING SPONTANEOUSLY
Publication/Patent Number: EP3733987A1 Publication Date: 2020-11-04 Application Number: 20170930.0 Filing Date: 2020-04-22 Inventor: Chang, Chin-lun   Chang, Cheng-han   Chang shih chieh   Assignee: Jenfu Machinery Co., Ltd.   IPC: E03F5/16 Abstract: An oil-water separator (44) with an oil discharge outlet (620) adjusting spontaneously includes a liquid storage tank (4) with grease (31) and wastewater (32), a telescopic pipe (5) in the liquid storage tank (4), and a floater unit (6) connected with the telescopic pipe (5). The liquid storage tank (4) comprises an inlet (421) for grease (31) and wastewater (32) input, and a water outlet (422) for wastewater (32) output. The floater unit (6) comprises at least one floater (61) floating between grease (31) and wastewater (32), and an isolation member (62) extending in the height direction between the floater (61) and the telescopic pipe (5). The isolation member (62) fluctuates along with height changes of wastewater (32) and includes an oil discharge outlet (620) for grease (31) entering the telescopic pipe (5). Therefore, an oil outlet (411), adjusting height spontaneously, is configured by the at least one floater (61), such that the overall height is reduced, a sufficient difference of levels of grease (31) and wastewater (32) is generated by the isolation member (62), thereby improving the oil-water separation effect.
14
US10868183B2
FinFET device and methods of forming the same
Publication/Patent Number: US10868183B2 Publication Date: 2020-12-15 Application Number: 16/177,072 Filing Date: 2018-10-31 Inventor: More, Shahaji B.   Chang shih chieh   Lee, Cheng-han   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.
15
US2020135913A1
FINFET DEVICE AND METHODS OF FORMING THE SAME
Publication/Patent Number: US2020135913A1 Publication Date: 2020-04-30 Application Number: 16/177,072 Filing Date: 2018-10-31 Inventor: More, Shahaji B.   Chang shih chieh   Lee, Cheng-han   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.
16
US2020006564A1
Semiconductor Device Having a Shaped Epitaxial Region
Publication/Patent Number: US2020006564A1 Publication Date: 2020-01-02 Application Number: 16/569,842 Filing Date: 2019-09-13 Inventor: Huang, Yi-min   Chang shih chieh   Lee, Cheng-han   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
17
US202006564A1
Semiconductor Device Having a Shaped Epitaxial Region
Publication/Patent Number: US202006564A1 Publication Date: 2020-01-02 Application Number: 20/191,656 Filing Date: 2019-09-13 Inventor: Chang shih chieh   Lee, Cheng-han   Huang, Yi-min   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
18
US2020098752A1
Semiconductor Device and Method
Publication/Patent Number: US2020098752A1 Publication Date: 2020-03-26 Application Number: 16/697,839 Filing Date: 2019-11-27 Inventor: Chang shih chieh   Lee, Cheng-han   Huang, Yi-min   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/088 Abstract: A process for manufacturing a semiconductor device and the resulting structure are presented. In an embodiment a source/drain region is grown. Once grown, the source/drain region is reshaped in order to remove facets. The reshaping may be performed using an etching process whereby a lateral etch rate of the source/drain region is larger than a vertical etch rate of the source/drain region.