Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1 US10638078B2
Counter, counting method and apparatus for image sensing
Publication/Patent Number: US10638078B2 Publication Date: 2020-04-28 Application Number: 15/995,143 Filing Date: 2018-06-01 Inventor: Yeh, Shang-fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Lee, Chih-lin   Yin, Chin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/374 Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters. A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common ...More Less
2 US2020174105A1
METHOD AND APPARATUS FOR A HYBRID TIME-OF-FLIGHT SENSOR WITH HIGH DYNAMIC RANGE
Publication/Patent Number: US2020174105A1 Publication Date: 2020-06-04 Application Number: 16/656,424 Filing Date: 2019-10-17 Inventor: Yin, Chin   Wu, Meng-hsiu   Lee, Chih-lin   Chao, Calvin Yi-ping   Yeh, Shang-fu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01S7/486 Abstract: Disclosed is a time-of-flight sensing apparatus and method. In one embodiment, a system for time-of-flight (TOF) sensing, comprising: a detector array comprising a plurality of single-photon avalanche detectors (SPADs); and a control circuit comprising at least two digital control arrays coupled to the detector array, a counter array coupled to the at least two digital control arrays, and a logical control unit coupled to the counter array and the at least two digital control arrays, wherein the detector array is configured to receive at least one reflected light pulse from a target, wherein a first digital control array, the counter array, and the logical control unit of the control circuit are configured to receive at least one avalanche pulses from each of the plurality of SPADs to determine a first distance between the detector array and the target in a first TOF mode, and wherein a second digital control array, the counter array, and the logical control unit of the control circuit are configured to receive the at least one avalanche pulse from the each of the plurality of SPADs to determine a second distance between the detector array and the target in a second TOF mode. Disclosed is a time-of-flight sensing apparatus and method. In one embodiment, a system for time-of-flight (TOF) sensing, comprising: a detector array comprising a plurality of single-photon avalanche detectors (SPADs); and a control circuit comprising at least two digital ...More Less
3 US2020119144A1
SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE
Publication/Patent Number: US2020119144A1 Publication Date: 2020-04-16 Application Number: 16/716,299 Filing Date: 2019-12-16 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh, Shang-fu   Lee, Chih-lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects. A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region ...More Less
4 US2020018642A1
Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing
Publication/Patent Number: US2020018642A1 Publication Date: 2020-01-16 Application Number: 16/454,358 Filing Date: 2019-06-27 Inventor: Yin, Chin   Lee, Chih-lin   Yeh, Shang-fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: G01J1/44 Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing. A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of ...More Less
5 US10510835B2
Semiconductor device with low random telegraph signal noise
Publication/Patent Number: US10510835B2 Publication Date: 2019-12-17 Application Number: 15/965,610 Filing Date: 2018-04-27 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh, Shang-fu   Lee, Chih-lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects. A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region ...More Less
6 US10277849B2
System and method for high-speed down-sampled CMOS image sensor readout
Publication/Patent Number: US10277849B2 Publication Date: 2019-04-30 Application Number: 15/941,431 Filing Date: 2018-03-30 Inventor: Chao, Calvin Yi-ping   Chang, Chin-hao   Chou, Kuo-yu   Yeh, Shang-fu   Lee, Chih-lin   Huang, Chiao-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/345 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation. A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality ...More Less
7 US2019333989A1
SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE
Publication/Patent Number: US2019333989A1 Publication Date: 2019-10-31 Application Number: 15/965,610 Filing Date: 2018-04-27 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh, Shang-fu   Lee, Chih-lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects. A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region ...More Less
8 US2019373200A1
COUNTER, COUNTING METHOD AND APPARATUS FOR IMAGE SENSING
Publication/Patent Number: US2019373200A1 Publication Date: 2019-12-05 Application Number: 15/995,143 Filing Date: 2018-06-01 Inventor: Yeh, Shang-fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Lee, Chih-lin   Yin, Chin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/376 Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters. A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common ...More Less
9 US9978796B2
Methods for forming dual-side illumination image sensor chips
Publication/Patent Number: US9978796B2 Publication Date: 2018-05-22 Application Number: 14/954,579 Filing Date: 2015-11-30 Inventor: Hsueh, Fu-lung   Chao, Calvin Yi-ping   Tu, Honyih   Liu, Chih-min   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H04N5/378 Abstract: A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light from a second direction opposite the first direction. A Dual-Side Illumination (DSI) image sensor chip includes a first image sensor chip configured to sense light from a first direction, and a second image sensor chip aligned to, and bonded to, the first image sensor chip. The second image sensor chip is configured to sense light ...More Less
10 US2018027648A1
INTERCONNECT STRUCTURE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2018027648A1 Publication Date: 2018-01-25 Application Number: 15/723,099 Filing Date: 2017-10-02 Inventor: Lee, Tsung-hsiung   Chao, Calvin Yi-ping   Hsueh, Fu-lung   Wu, Jiun-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H05K3/00 Abstract: A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via. A method for manufacturing an interconnect structure is provided. The method includes the following steps. An opening is through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor ...More Less
11 US9955096B2
System and method for high-speed down-sampled CMOS image sensor readout
Publication/Patent Number: US9955096B2 Publication Date: 2018-04-24 Application Number: 15/076,983 Filing Date: 2016-03-22 Inventor: Huang, Chiao-yi   Chou, Kuo-yu   Lee, Chih-lin   Chang, Chin-hao   Yeh, Shang-fu   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/378 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation. A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality ...More Less
12 US2018227531A1
SYSTEM AND METHOD FOR HIGH-SPEED DOWN-SAMPLED CMOS IMAGE SENSOR READOUT
Publication/Patent Number: US2018227531A1 Publication Date: 2018-08-09 Application Number: 15/941,431 Filing Date: 2018-03-30 Inventor: Huang, Chiao-yi   Lee, Chih-lin   Yeh, Shang-fu   Chou, Kuo-yu   Chang, Chin-hao   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/378 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation. A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality ...More Less
13 US10165208B2
Method for reducing blooming in image sensor during idle period
Publication/Patent Number: US10165208B2 Publication Date: 2018-12-25 Application Number: 15/011,951 Filing Date: 2016-02-01 Inventor: Chou, Kuo-yu   Chao, Calvin Yi-ping   Hsueh, Fu-lung   Tu, Honyih   Sze, Jhy-jyi   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/00 Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image. Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the ...More Less
14 TW201801521A
System and method for high-speed down sampled CMOS image sensor readout
Publication/Patent Number: TW201801521A Publication Date: 2018-01-01 Application Number: 105135352 Filing Date: 2016-11-01 Inventor: Chou, Kuo-yu   Chang, Chin-hao   Yeh, Shang-fu   Huang, Chiao-yi   Chao, Calvin Yi-ping   Lee, Chih-lin   Assignee: Taiwan Semiconductor Manufacturing Company Ltd.   IPC: H04N5/3745 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation. A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality ...More Less
15 US10096645B2
Method and apparatus for image sensor packaging
Publication/Patent Number: US10096645B2 Publication Date: 2018-10-09 Application Number: 15/193,812 Filing Date: 2016-06-27 Inventor: Chen, Szu-ying   Liu, Ping-yin   Chao, Calvin Yi-ping   Wang, Tzu-jui   Liu, Jen-cheng   Yaung, Dun-nian   Chao, Lan-lin   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/00 Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond pad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding strength between the sensor and the ASIC. Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a ...More Less
16 US9838620B2
Sensor having depth sensing pixel and method of using the same
Publication/Patent Number: US9838620B2 Publication Date: 2017-12-05 Application Number: 15/404,908 Filing Date: 2017-01-12 Inventor: Chao, Calvin Yi-ping   Chou, Kuo-yu   Liu, Chih-min   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: H01L27/146 Abstract: A sensor includes a plurality of image sensors, wherein each image sensor of the plurality of image sensors is configured to detect a first spectrum of light. The sensor further includes a depth sensing pixel bonded to each image sensor of the plurality of image sensors, wherein the depth sensing pixel is configured to detect a second spectrum of light different from the first spectrum. A sensor includes a plurality of image sensors, wherein each image sensor of the plurality of image sensors is configured to detect a first spectrum of light. The sensor further includes a depth sensing pixel bonded to each image sensor of the plurality of image sensors, wherein ...More Less
17 US2017134670A1
SENSOR HAVING DEPTH SENSING PIXEL AND METHOD OF USING THE SAME
Publication/Patent Number: US2017134670A1 Publication Date: 2017-05-11 Application Number: 15/404,908 Filing Date: 2017-01-12 Inventor: Chao, Calvin Yi-ping   Chou, Kuo-yu   Liu, Chih-min   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: H04N5/33 Abstract: A sensor includes a plurality of image sensors, wherein each image sensor of the plurality of image sensors is configured to detect a first spectrum of light. The sensor further includes a depth sensing pixel bonded to each image sensor of the plurality of image sensors, wherein the depth sensing pixel is configured to detect a second spectrum of light different from the first spectrum. A sensor includes a plurality of image sensors, wherein each image sensor of the plurality of image sensors is configured to detect a first spectrum of light. The sensor further includes a depth sensing pixel bonded to each image sensor of the plurality of image sensors, wherein ...More Less