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1
US2020176260A1
FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
Publication/Patent Number: US2020176260A1 Publication Date: 2020-06-04 Application Number: 16/265,747 Filing Date: 2019-02-01 Inventor: Hung, Min-hsiu   Chang, Chien   Chao yi hsiang   Huang, Hung-yi   Chang, Chih-wei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/285 Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.
2
US2020335597A1
SEMICONDUCTOR DEVICE WITH LOW RESISTIVITY CONTACT STRUCTURE
Publication/Patent Number: US2020335597A1 Publication Date: 2020-10-22 Application Number: 16/914,638 Filing Date: 2020-06-29 Inventor: Hung, Min-hsiu   Chao yi hsiang   Yeh, Kuan-yu   Lin, Kan-ju   Nieh, Chun-wen   Huang, Huang-yi   Chang, Chih-wei   Su, Ching-hwanq   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/45 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.
3
US10685842B2
Selective formation of titanium silicide and titanium nitride by hydrogen gas control
Publication/Patent Number: US10685842B2 Publication Date: 2020-06-16 Application Number: 15/983,216 Filing Date: 2018-05-18 Inventor: Chang, Cheng-wei   Lin, Kao-feng   Hung, Min-hsiu   Chao yi hsiang   Huang, Huang-yi   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/285 Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
4
US10700177B2
Semiconductor device with low resistivity contact structure and method for forming the same
Publication/Patent Number: US10700177B2 Publication Date: 2020-06-30 Application Number: 15/964,352 Filing Date: 2018-04-27 Inventor: Hung, Min-hsiu   Chao yi hsiang   Yeh, Kuan-yu   Lin, Kan-ju   Nieh, Chun-wen   Huang, Huang-yi   Chang, Chih-wei   Su, Ching-hwanq   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L29/45 Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
5
US2020294807A1
SELECTIVE FORMATION OF TITANIUM SILICIDE AND TITANIUM NITRIDE BY HYDROGEN GAS CONTROL
Publication/Patent Number: US2020294807A1 Publication Date: 2020-09-17 Application Number: 16/887,218 Filing Date: 2020-05-29 Inventor: Chang, Cheng-wei   Lin, Kao-feng   Hung, Min-hsiu   Chao yi hsiang   Huang, Huang-yi   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/285 Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
6
US202020583A1
FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL-SEMICONDUCTOR COMPOUND REGION
Publication/Patent Number: US202020583A1 Publication Date: 2020-01-16 Application Number: 20/181,603 Filing Date: 2018-07-13 Inventor: Chang, Chih-wei   Tsai, Ming-hsing   Su, Ching-hwanq   Chu, Li-wei   Chao yi hsiang   Hung, Min-hsiu   Li, Ya-huei   Liao, Yu-hsiang   Huang, Hung-yi   Yeh, Kuan-yu   Lin, Kan-ju   Chuang, Chi-hung   Nieh, Chun-wen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
7
US2020020583A1
FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL-SEMICONDUCTOR COMPOUND REGION
Publication/Patent Number: US2020020583A1 Publication Date: 2020-01-16 Application Number: 16/034,843 Filing Date: 2018-07-13 Inventor: Chao yi hsiang   Hung, Min-hsiu   Nieh, Chun-wen   Li, Ya-huei   Liao, Yu-hsiang   Chu, Li-wei   Lin, Kan-ju   Yeh, Kuan-yu   Chuang, Chi-hung   Chang, Chih-wei   Su, Ching-hwanq   Huang, Hung-yi   Tsai, Ming-hsing   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
8
US2019355585A1
SELECTIVE FORMATION OF TITANIUM SILICIDE AND TITANIUM NITRIDE BY HYDROGEN GAS CONTROL
Publication/Patent Number: US2019355585A1 Publication Date: 2019-11-21 Application Number: 15/983,216 Filing Date: 2018-05-18 Inventor: Chang, Cheng-wei   Lin, Kao-feng   Hung, Min-hsiu   Chao yi hsiang   Huang, Huang-yi   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/285 Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
9
US201997012A1
SEMICONDUCTOR DEVICE WITH LOW RESISTIVITY CONTACT STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US201997012A1 Publication Date: 2019-03-28 Application Number: 20/181,596 Filing Date: 2018-04-27 Inventor: Huang, Huang-yi   Chang, Chih-wei   Su, Ching-hwanq   Chao yi hsiang   Hung, Min-hsiu   Nieh, Chun-wen   Yeh, Kuan-yu   Lin, Kan-ju   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/3205 Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
10
US2019097012A1
SEMICONDUCTOR DEVICE WITH LOW RESISTIVITY CONTACT STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2019097012A1 Publication Date: 2019-03-28 Application Number: 15/964,352 Filing Date: 2018-04-27 Inventor: Hung, Min-hsiu   Chao yi hsiang   Yeh, Kuan-yu   Lin, Kan-ju   Nieh, Chun-wen   Huang, Huang-yi   Chang, Chih-wei   Su, Ching-hwanq   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/45 Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
11
TWI599500B
Fixing mechanism for fixing an electronic device and related electronic apparatus
Publication/Patent Number: TWI599500B Publication Date: 2017-09-21 Application Number: 102109085 Filing Date: 2013-03-14 Inventor: Chao, Yi Hsiang   Assignee: Wistron Corporation   IPC: B60R11/02 Abstract: The present invention discloses a fixing mechanism including a base
12
TWI499611B
CONJUGATED POLYMER COMPOUND
Publication/Patent Number: TWI499611B Publication Date: 2015-09-11 Application Number: 102141537 Filing Date: 2013-11-14 Inventor: Wang, Chin Li   Tsai, Ming Chi   Lin, Ching Yao   Hsu, Chain Shu   Wang, Chien Lung   Wu, Jhong Sian   Chao, Yi Hsiang   Jheng, Jyun Fong   Assignee: National Chiao Tung University   IPC: C08G61/12 Abstract: The present invention provides a conjugated polymer compound
13
TW201518335A
CONJUGATED POLYMER COMPOUND
Publication/Patent Number: TW201518335A Publication Date: 2015-05-16 Application Number: 102141537 Filing Date: 2013-11-14 Inventor: Wang, Chin Li   Tsai, Ming Chi   Lin, Ching Yao   Hsu, Chain Shu   Wang, Chien Lung   Wu, Jhong Sian   Chao, Yi Hsiang   Jheng, Jyun Fong   Assignee: National Chiao Tung University   IPC: C08G61/12 Abstract: The present invention provides a conjugated polymer compound
14
US9217063B2
Conjugated polymer compound
Publication/Patent Number: US9217063B2 Publication Date: 2015-12-22 Application Number: 14/502,879 Filing Date: 2014-09-30 Inventor: Hsu, Chain-shu   Lin, Ching-yao   Wang, Chien-lung   Wu, Jhong-sian   Chao yi hsiang   Jheng, Jyun-fong   Tsai, Ming-chi   Wang, Chin-li   Assignee: NATIONAL CHIAO TUNG UNIVERSITY   IPC: C08G65/38 Abstract: A conjugated polymer compound is disclosed. The conjugated polymer compound includes a conjugated polymeric main chain; and a porphyrin compound having absorption in a blue light region of solar radiation, and is bonded to the polymeric main chain to form a side chain on the polymeric main chain.
15
US2015133617A1
CONJUGATED POLYMER COMPOUND
Publication/Patent Number: US2015133617A1 Publication Date: 2015-05-14 Application Number: 14/502,879 Filing Date: 2014-09-30 Inventor: Hsu, Chain-shu   Lin, Ching-yao   Wang, Chien-lung   Wu, Jhong-sian   Chao yi hsiang   Jheng, Jyun-fong   Tsai, Ming-chi   Wang, Chin-li   Assignee: NATIONAL CHIAO TUNG UNIVERSITY   IPC: C08G75/00 Abstract: A conjugated polymer compound is disclosed. The conjugated polymer compound includes a conjugated polymeric main chain; and a porphyrin compound having absorption in a blue light region of solar radiation, and is bonded to the polymeric main chain to form a side chain on the polymeric main chain.
16
TW201434689A
Fixing mechanism for fixing an electronic device and related electronic apparatus
Publication/Patent Number: TW201434689A Publication Date: 2014-09-16 Application Number: 102109085 Filing Date: 2013-03-14 Inventor: Chao, Yi Hsiang   Assignee: Wistron Corporation   IPC: B60R11/02 Abstract: The present invention discloses a fixing mechanism including a base
17
US2014268622A1
FIXING MECHANISM FOR FIXING AN PORTABLE ELECTRONIC DEVICE AND RELATED ELECTRONIC APPARATUS
Publication/Patent Number: US2014268622A1 Publication Date: 2014-09-18 Application Number: 14/072,792 Filing Date: 2013-11-06 Inventor: Chao yi hsiang   Assignee: Wistron Corporation   IPC: H05K5/02 Abstract: The present invention discloses a fixing mechanism including a base, a cover, a connecting component, at least one resilient component and a pushing component. The base is for containing a portable electronic device. The cover is pivoted to the base. The connecting component is disposed on the base for engaging with the cover. The at least one resilient component is disposed on the base. The pushing component is connected to the at least one resilient component and the connecting component, the pushing component is driven to move in a first direction as the portable electronic device is installed on the base, so as to drive the connecting component to separate from the cover, so that the cover pivots in a first pivoting direction relative to the base to engage with the end of the portable electronic device.
18
US2012069518A1
PORTABLE ELECTRONIC DEVICE
Publication/Patent Number: US2012069518A1 Publication Date: 2012-03-22 Application Number: 13/033,841 Filing Date: 2011-02-24 Inventor: Hsu, Hsin-an   Lin, Jin-de   Chao yi hsiang   Assignee: HSU, Hsin-An   Lin, Jin-De   Chao yi hsiang   IPC: H05K5/02 Abstract: A portable electronic device includes a computer housing and a cover, wherein the computer housing includes a housing side portion and a housing surface portion neighboring to the housing side portion, an accommodating recess, a pivot slide recess, and a hook slide recess. The cover includes a cover body, a pivoting portion and a hook portion. The housing side portion and the housing surface portion are recessed together so as to define the accommodating recess. The accommodating recess is provided with two positioning areas and a socket area in connection with the two positioning areas, and that the socket area is provided with an extension socket. The cover body covers, selectively, the accommodating recess, and that the pivoting portion can slide and can be pivotally arranged in the pivot slide recess, while the hook portion can slide and can be arranged in the hook slide recess.