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1 | US10726902B2 |
Circuit for controlling memory and associated method
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Publication/Patent Number: US10726902B2 | Publication Date: 2020-07-28 | Application Number: 16/056,802 | Filing Date: 2018-08-07 | Inventor： Chen chung ching Lin, Chen-nan Chuang, Che-wei | Assignee: MEDIATEK INC. | IPC: G11C11/406 | Abstract: A circuit for controlling a memory includes a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator generates at least one frequency control signal. The clock generator, coupled to the frequency generator, increases or decreases the frequency of a clock signal by a multiple number of times according to the frequency control signal, such that the frequency of the clock signal is adjusted from an initial frequency to a target frequency. The memory controller, coupled to the clock generator, receives the clock signal and controls the memory according to the clock signal. | |||
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2 | US2019245006A1 |
MICRO LED DISPLAY DEVICE
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Publication/Patent Number: US2019245006A1 | Publication Date: 2019-08-08 | Application Number: 16/136,233 | Filing Date: 2018-09-19 | Inventor： Chen chung ching Tsai, Ping-yu | Assignee: YingLight Technology Co. Ltd. | IPC: H01L33/50 | Abstract: A micro LED display device includes a micro LED array, a light transmission layer, a color filter and a polarizer. The micro LED array includes a plurality of micro LEDs. The light transmission layer is located above the micro LED array. The color filter is located above the light transmission layer. The polarizer is located above the color filter. | |||
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3 | TW201931360A |
Circuit for controlling memory and associated method
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Publication/Patent Number: TW201931360A | Publication Date: 2019-08-01 | Application Number: 107100498 | Filing Date: 2018-01-05 | Inventor： Lin, Chen-nan Chen chung ching Chuang, Che-wei | Assignee: MStar Semiconductor, Inc. | IPC: G11C8/18 | Abstract: The present invention discloses a circuit for controlling a memory, wherein the circuit comprises a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator is used to receive a start frequency parameter, an end frequency parameter and a frequency adjusting rate parameter to generate at least one frequency control signal. The clock generator is coupled to the frequency parameter generator, and is used to adjust a frequency of a clock signal according to the frequency control signal. The memory controller is coupled to the clock generator, and is used to receive the clock signal, and control the memory according to the clock signal. | |||
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4 | US2019214075A1 |
CIRCUIT FOR CONTROLLING MEMORY AND ASSOCIATED METHOD
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Publication/Patent Number: US2019214075A1 | Publication Date: 2019-07-11 | Application Number: 16/056,802 | Filing Date: 2018-08-07 | Inventor： Chen chung ching Lin, Chen-nan Chuang, Che-wei | Assignee: MStar Semiconductor, Inc. | IPC: G11C11/406 | Abstract: A circuit for controlling a memory includes a frequency parameter generator, a clock generator and a memory controller. The frequency parameter generator generates at least one frequency control signal. The clock generator, coupled to the frequency generator, increases or decreases the frequency of a clock signal by a multiple number of times according to the frequency control signal, such that the frequency of the clock signal is adjusted from an initial frequency to a target frequency. The memory controller, coupled to the clock generator, receives the clock signal and controls the memory according to the clock signal. | |||
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5 | US10090061B2 |
Memory test data generating circuit and method
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Publication/Patent Number: US10090061B2 | Publication Date: 2018-10-02 | Application Number: 15/138,456 | Filing Date: 2016-04-26 | Inventor： Chang, Qi-xin Lin, Chen-nan Chen chung ching | Assignee: MSTAR SEMICONDUCTOR, INC. | IPC: H03M13/03 | Abstract: A memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series. | |||
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6 | US2018267726A1 |
MEMORY SPACE MANAGEMENT AND MEMORY ACCESS CONTROL METHOD AND APPARATUS
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Publication/Patent Number: US2018267726A1 | Publication Date: 2018-09-20 | Application Number: 15/908,888 | Filing Date: 2018-03-01 | Inventor： Sun, Ming Yong Chang, Yung Chen chung ching Lo, Yi-hao | Assignee: MStar Semiconductor, Inc. | IPC: G06F3/06 | Abstract: Memory space management and memory access control method and apparatus are provided. The method includes: upon receiving an access request, acquiring an access address and an accessor identifier in the access request; checking a current state of a memory space pointed by the access address to obtain a check result, wherein the state of the memory space includes a first state and a second state; determining whether the accessor identifier belongs to an access permission set among a plurality of access permission sets that corresponds to the check result; and generating an instruction according to the check result, wherein the instruction indicates whether or not the accessor is permitted to access the memory space. With the above method, the invention reduces resource waste and system costs. | |||
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7 | TW201833775A |
Storage space management and memory access control method and apparatus
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Publication/Patent Number: TW201833775A | Publication Date: 2018-09-16 | Application Number: 106114891 | Filing Date: 2017-05-05 | Inventor： Chen chung ching Chang, Yung Sun, Ming-yong Lo, Yi-hao | Assignee: MStar Semiconductor, Inc. | IPC: G06F12/02 | Abstract: The present invention discloses a memory space management and a memory access control method and an apparatus. The method comprises: obtaining an access address and an accessor identification in the access request upon receiving an access request; checking the current state of the memory space pointed to by the access address to obtain an inspection result, wherein the state of the memory space including a first state and a second state; checking whether the accessor identification belongs to a permitted access set among a plurality of permitted access sets that corresponds to the inspection result; generating an instruction based on the checking result, wherein the instruction is used to indicate that the memory space is allowed or not allowed to be accessed by the accessor. In the above-described manner, the present invention can reduce the waste of the storage resources and reduce the system cost. | |||
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8 | TWI564905B |
Memory self-testing device and method thereof
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Publication/Patent Number: TWI564905B | Publication Date: 2017-01-01 | Application Number: 104106618 | Filing Date: 2015-03-03 | Inventor： Lin, Chen Nan Chen, Chung Ching Lo, Yi Hao | Assignee: MStar Semiconductor, Inc | IPC: G11C29/08 | Abstract: A memory self-testing device for testing a plurality of memory control units comprises a test control unit | |||
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9 | TWI569278B |
CIRCUIT FOR GENERATING MEMORY TEST DATA AND METHOD THEREOF
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Publication/Patent Number: TWI569278B | Publication Date: 2017-02-01 | Application Number: 104113505 | Filing Date: 2015-04-28 | Inventor： Lin, Chen Nan Chen, Chung Ching Chang, Qi Xin | Assignee: MStar Semiconductor, Inc | IPC: G11C29/04 | Abstract: A circuit for generating memory test data and its associated method are disclosed. The memory test data are coupled | |||
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10 | TWI588841B |
Memory controller and associated signal generating method
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Publication/Patent Number: TWI588841B | Publication Date: 2017-06-21 | Application Number: 102122579 | Filing Date: 2013-06-25 | Inventor： Lin, Chen Nan Chang, Yung Chen, Chung Ching Wu, Zong Han | Assignee: MStar Semiconductor, Inc | IPC: G11C7/22 | Abstract: A memory controller and associated signal generating method are provided. The sequence of commands is properly arranged to enlarge latching interval of a address signal and a bank signal. Thus | |||
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11 | US9697148B2 |
Apparatus and method for managing memory
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Publication/Patent Number: US9697148B2 | Publication Date: 2017-07-04 | Application Number: 14/876,043 | Filing Date: 2015-10-06 | Inventor： Chang, Yung Lin, Chen-nan Chen chung ching | Assignee: MStar Semiconductor, Inc. | IPC: G11C8/00 | Abstract: An apparatus for managing a memory having a plurality of command/address pins is provided. The apparatus includes a command generating module and a control module. The command generating module generates a set of target commands. The set of target commands include a plurality of command groups. Each of the command groups corresponds to at least one command/address pin of the plurality of command/address pins. It is known that the memory accesses the set of target commands from the plurality of command/address pins at a target time point. The control module controls the command groups to have different transition times prior to the target time points when the command groups are transmitted on the plurality of command/address pins. | |||
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12 | US9589671B2 |
Self testing device for memory channels and memory control units and method thereof
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Publication/Patent Number: US9589671B2 | Publication Date: 2017-03-07 | Application Number: 15/057,203 | Filing Date: 2016-03-01 | Inventor： Chen chung ching Lin, Chen-nan Lo, Yi-hao | Assignee: MStar Semiconductor, Inc. | IPC: G11C7/00 | Abstract: A memory self-testing device for testing a plurality of memory control units includes: a test control unit, coupled to the memory control units, generating a plurality of access request signals and a plurality of sets of data; a channel control unit, coupled to the test control unit and the memory control units, determining a leading feedback signal among a plurality of feedback signals; and a data control unit, coupled to the test control unit and the memory control units, storing the sets of data, and transmitting the sets of data to the memory control units according to a plurality of read/write signals. The feedback signals and the read/write signals are generated by the memory control units in response to the access request signals. The test control units generate the sets of data according to the leading feedback signal. | |||
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13 | TWI550403B |
Memory controller and associatted memory address generating method
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Publication/Patent Number: TWI550403B | Publication Date: 2016-09-21 | Application Number: 102111928 | Filing Date: 2013-04-02 | Inventor： Lin, Chen Nan Chang, Yung Chen, Chung Ching | Assignee: MStar Semiconductor, Inc | IPC: G06F12/08 | Abstract: A memory controller connects to a DDR DRAM and a fetching unit. The controller unit includes: a processing unit capable of receiving a system address; and a mapping unit included in the processing unit capable of transferring the system address to a memory address and then transmitting the memory address to the DDR DRAM. A burst length of the DDR DRAM is L and L=2x. A (x+1)th bit of the memory address from LSB is set to be included in a bank group address of the memory address. | |||
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14 | TW201638964A |
CIRCUIT FOR GENERATING MEMORY TEST DATA AND METHOD THEREOF
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Publication/Patent Number: TW201638964A | Publication Date: 2016-11-01 | Application Number: 104113505 | Filing Date: 2015-04-28 | Inventor： Lin, Chen Nan Chen, Chung Ching Chang, Qi Xin | Assignee: MStar Semiconductor, Inc | IPC: G11C29/04 | Abstract: A circuit for generating memory test data and its associated method are disclosed. The memory test data are coupled | |||
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15 | TW201633324A |
Memory self-testing device and method thereof
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Publication/Patent Number: TW201633324A | Publication Date: 2016-09-16 | Application Number: 104106618 | Filing Date: 2015-03-03 | Inventor： Lin, Chen Nan Chen, Chung Ching Lo, Yi Hao | Assignee: MStar Semiconductor, Inc | IPC: G11C29/08 | Abstract: A memory self-testing device for testing a plurality of memory control units comprises a test control unit | |||
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16 | US2016260500A1 |
MEMORY SELF-TESTING DEVICE AND METHOD THEREOF
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Publication/Patent Number: US2016260500A1 | Publication Date: 2016-09-08 | Application Number: 15/057,203 | Filing Date: 2016-03-01 | Inventor： Chen chung ching Lin, Chen-nan Lo, Yi-hao | Assignee: MStar Semiconductor, Inc. | IPC: G11C29/04 | Abstract: A memory self-testing device for testing a plurality of memory control units includes: a test control unit, coupled to the memory control units, generating a plurality of access request signals and a plurality of sets of data; a channel control unit, coupled to the test control unit and the memory control units, determining a leading feedback signal among a plurality of feedback signals; and a data control unit, coupled to the test control unit and the memory control units, storing the sets of data, and transmitting the sets of data to the memory control units according to a plurality of read/write signals. The feedback signals and the read/write signals are generated by the memory control units in response to the access request signals. The test control units generate the sets of data according to the leading feedback signal. | |||
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17 | US9424902B2 |
Memory controller and associated method for generating memory address
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Publication/Patent Number: US9424902B2 | Publication Date: 2016-08-23 | Application Number: 14/228,390 | Filing Date: 2014-03-28 | Inventor： Chen chung ching Lin, Chen-nan Chang, Yung | Assignee: MStar Semiconductor, Inc. | IPC: G06F12/00 | Abstract: A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2x (where L and x are positive integers), an (x+1)th bit of the memory address from a least significant bit (LSB) is included in a bank group address of the memory address. | |||
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18 | US9355744B2 |
Dynamic memory signal phase tracking method and associated control circuit
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Publication/Patent Number: US9355744B2 | Publication Date: 2016-05-31 | Application Number: 14/321,039 | Filing Date: 2014-07-01 | Inventor： Chang, Yung Lin, Chen-nan Chen chung ching | Assignee: MSTAR SEMICONDUCTOR, INC. | IPC: G06F12/00 | Abstract: A dynamic memory signal phase tracking method is provided. The method, applied to a memory controller that accesses a memory module, includes: issuing a memory access command and an access request to an arbiter to request for an access right of the memory module; when the access right is obtained, forwarding the memory access command to the memory module and asserting a flag signal; during a period of asserting the flag signal, sequentially using a plurality of candidate delay phases to adjust a memory signal for latching test data from the memory module, determining a delay phase according to latching results corresponding to the candidate delay phases, and recording the determined delay phases; updating an optimal delay phase according to the determined delay phase; and accessing the memory module according to the updated optimal delay phase. | |||
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19 | US2016124648A1 |
Apparatus and Method for Managing Memory
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Publication/Patent Number: US2016124648A1 | Publication Date: 2016-05-05 | Application Number: 14/876,043 | Filing Date: 2015-10-06 | Inventor： Chang, Yung Lin, Chen-nan Chen chung ching | Assignee: MStar Semiconductor, Inc. | IPC: G06F3/06 | Abstract: An apparatus for managing a memory having a plurality of command/address pins is provided. The apparatus includes a command generating module and a control module. The command generating module generates a set of target commands. The set of target commands include a plurality of command groups. Each of the command groups corresponds to at least one command/address pin of the plurality of command/address pins. It is known that the memory accesses the set of target commands from the plurality of command/address pins at a target time point. The control module controls the command groups to have different transition times prior to the target time points when the command groups are transmitted on the plurality of command/address pins. | |||
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20 | US2016322117A1 |
Memory Test Data Generating Circuit and Method
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Publication/Patent Number: US2016322117A1 | Publication Date: 2016-11-03 | Application Number: 15/138,456 | Filing Date: 2016-04-26 | Inventor： Chang, Qi-xin Lin, Chen-nan Chen chung ching | Assignee: MStar Semiconductor, Inc. | IPC: G11C29/38 | Abstract: A memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series. |
3.Current Quota