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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10643863B2
Semiconductor package and method of manufacturing the same
Publication/Patent Number: US10643863B2 Publication Date: 2020-05-05 Application Number: 15/685,864 Filing Date: 2017-08-24 Inventor: Yen, You-lung   Chen kuang hsiung   Liang, Shing-cheng   Hsu, Pei-yu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/48 Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.
2 US2020080841A1
OPTICAL MODULE AND METHOD OF MAKING THE SAME
Publication/Patent Number: US2020080841A1 Publication Date: 2020-03-12 Application Number: 16/683,117 Filing Date: 2019-11-13 Inventor: Chen, Ying-chung   Chan, Hsun-wei   Lai, Lu-ming   Chen kuang hsiung   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: G01C3/08 Abstract: An optical module includes: a carrier; an optical element disposed on the upper side of the carrier; and a housing disposed on the upper side of the carrier, the housing defining an aperture exposing at least a portion of the optical element, an outer sidewall of the housing including at least one singulation portion disposed on the upper side of the carrier, wherein the singulation portion of the housing is a first portion of the housing, and wherein the housing further includes a second portion and a surface of the singulation portion of the housing is rougher than a surface of the second portion of the housing.
3 US10573624B2
Semiconductor device package and method of manufacturing the same
Publication/Patent Number: US10573624B2 Publication Date: 2020-02-25 Application Number: 16/194,265 Filing Date: 2018-11-16 Inventor: Chen, Tien-szu   Chen kuang hsiung   Wang, Sheng-ming   Wang, I-cheng   Syu, Wun-jheng   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L25/065 Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.
4 US10734337B2
Semiconductor package device having glass transition temperature greater than binding layer temperature
Publication/Patent Number: US10734337B2 Publication Date: 2020-08-04 Application Number: 16/293,606 Filing Date: 2019-03-05 Inventor: Chen kuang hsiung   Tsai, Yu-hsuan   Lee, Yu-ying   Wang, Sheng-ming   Syu, Wun-jheng   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/28 Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
5 US2019067036A1
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2019067036A1 Publication Date: 2019-02-28 Application Number: 15/685,864 Filing Date: 2017-08-24 Inventor: Yen, You-lung   Chen kuang hsiung   Liang, Shing-cheng   Hsu, Pei-yu   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L21/56 Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.
6 US10508910B2
Optical module and method of making the same
Publication/Patent Number: US10508910B2 Publication Date: 2019-12-17 Application Number: 14/975,083 Filing Date: 2015-12-18 Inventor: Chen, Ying-chung   Chan, Hsun-wei   Lai, Lu-ming   Chen kuang hsiung   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: G01C3/08 Abstract: An optical module includes a carrier, a light source disposed on an upper side of the carrier, an optical sensor disposed on the upper side of the carrier, and a housing disposed on the upper side of the carrier over the light source and the optical sensor. The housing defines a first aperture exposing at least a portion of the light source and a second aperture exposing at least a portion of the optical sensor. An outer sidewall of the housing includes at least one singulation portion adjacent to the upper side of the carrier and perpendicular to the upper side of the carrier.
7 US201967036A1
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US201967036A1 Publication Date: 2019-02-28 Application Number: 20/171,568 Filing Date: 2017-08-24 Inventor: Chen kuang hsiung   Liang, Shing-cheng   Yen, You-lung   Hsu, Pei-yu   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/482 Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.
8 US10446411B2
Semiconductor device package with a conductive post
Publication/Patent Number: US10446411B2 Publication Date: 2019-10-15 Application Number: 16/102,527 Filing Date: 2018-08-13 Inventor: Chen, Tien-szu   Chen kuang hsiung   Wang, Sheng-ming   Lee, Yu-ying   Peng, Yu-tzu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/48 Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.
9 US2019088626A1
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2019088626A1 Publication Date: 2019-03-21 Application Number: 16/194,265 Filing Date: 2018-11-16 Inventor: Chen, Tien-szu   Chen kuang hsiung   Wang, Sheng-ming   Wang, I-cheng   Syu, Wun-jheng   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L25/065 Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.
10 US201988626A1
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US201988626A1 Publication Date: 2019-03-21 Application Number: 20/181,619 Filing Date: 2018-11-16 Inventor: Chen kuang hsiung   Wang, Sheng-ming   Chen, Tien-szu   Wang, I-cheng   Syu, Wun-jheng   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L25/065 Abstract: A semiconductor device package includes: (1) a first circuit layer including a first surface and a second surface opposite to the first surface; (2) at least one electrical element disposed over the first surface of the first circuit layer and electrically connected to the first circuit layer; (3) a first molding layer disposed over the first surface of the first circuit layer, wherein the first molding layer encapsulates an edge of the at least one electrical element; (4) first electronic components disposed over the second surface of the first circuit layer and electrically connected to the first circuit layer; and (5) a second molding layer disposed over the second surface of the first circuit layer and encapsulating the first electronic components, wherein the first molding layer and the second molding layer include different molding materials.
11 US10224298B2
Semiconductor package device having glass transition temperature greater than binding layer temperature
Publication/Patent Number: US10224298B2 Publication Date: 2019-03-05 Application Number: 15/649,474 Filing Date: 2017-07-13 Inventor: Chen kuang hsiung   Tsai, Yu-hsuan   Lee, Yu-ying   Wang, Sheng-ming   Syu, Wun-jheng   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/28 Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).
12 US2019198469A1
SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2019198469A1 Publication Date: 2019-06-27 Application Number: 16/293,606 Filing Date: 2019-03-05 Inventor: Chen kuang hsiung   Tsai, Yu-hsuan   Lee, Yu-ying   Wang, Sheng-ming   Syu, Wun-jheng   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/00 Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
13 US10515884B2
Substrate having a conductive structure within photo-sensitive resin
Publication/Patent Number: US10515884B2 Publication Date: 2019-12-24 Application Number: 14/624,388 Filing Date: 2015-02-17 Inventor: Chen, Tien-szu   Chen kuang hsiung   Wang, Sheng-ming   Lee, Yu-ying   Tsai, Li-chuan   Lee, Chih-cheng   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/498 Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.
14 US201868962A1
SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US201868962A1 Publication Date: 2018-03-08 Application Number: 20/171,564 Filing Date: 2017-07-13 Inventor: Chen kuang hsiung   Chen, Tien-szu   Chen kuang hsiung   Wang, Yi-wei   Wang, I-cheng   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/31 Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).
15 US9911702B2
Semiconductor package structure and fabrication method thereof
Publication/Patent Number: US9911702B2 Publication Date: 2018-03-06 Application Number: 14/268,981 Filing Date: 2014-05-02 Inventor: Lee, Yu-ying   Chen kuang hsiung   Wang, Sheng-ming   Chen, Tien-szu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/498 Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.
16 US2018145037A1
SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
Publication/Patent Number: US2018145037A1 Publication Date: 2018-05-24 Application Number: 15/873,784 Filing Date: 2018-01-17 Inventor: Lee, Yu-ying   Chen kuang hsiung   Wang, Sheng-ming   Chen, Tien-szu   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L21/56 Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.
17 US10002843B2
Semiconductor substrate structure, semiconductor package and method of manufacturing the same
Publication/Patent Number: US10002843B2 Publication Date: 2018-06-19 Application Number: 14/667,317 Filing Date: 2015-03-24 Inventor: Lee, Yu-ying   Wang, Sheng-ming   Chen kuang hsiung   Chen, Tien-szu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H05K3/10 Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.
18 US10103110B2
Semiconductor package structure and fabrication method thereof
Publication/Patent Number: US10103110B2 Publication Date: 2018-10-16 Application Number: 15/873,784 Filing Date: 2018-01-17 Inventor: Chen, Tien-szu   Wang, Sheng-ming   Chen kuang hsiung   Lee, Yu-ying   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L21/00 Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.
19 US9984989B2
Semiconductor substrate and semiconductor package structure
Publication/Patent Number: US9984989B2 Publication Date: 2018-05-29 Application Number: 14/855,849 Filing Date: 2015-09-16 Inventor: Lee, Yu-ying   Chen kuang hsiung   Wang, Sheng-ming   Chen, Tien-szu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/498 Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.
20 US10049976B2
Semiconductor substrate and manufacturing method thereof
Publication/Patent Number: US10049976B2 Publication Date: 2018-08-14 Application Number: 15/006,306 Filing Date: 2016-01-26 Inventor: Lee, Yu-ying   Chen kuang hsiung   Wang, Sheng-ming   Lee, Chun-che   Chen, Tien-szu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L21/48 Abstract: A semiconductor substrate includes an insulating layer and a conductive circuit layer embedded at a surface of the insulating layer. The conductive circuit layer includes a first portion and a second portion. The first portion includes a bonding pad and one portion of a conductive trace, and the second portion includes another portion of the conductive trace. An upper surface of the first portion is not coplanar with an upper surface of the second portion. A semiconductor packaging structure includes the semiconductor substrate.