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1
US2020227253A1
SUPERCRITICAL DRYING APPARATUS AND METHOD OF DRYING SUBSTRATE USING THE SAME
Publication/Patent Number: US2020227253A1 Publication Date: 2020-07-16 Application Number: 16/561,078 Filing Date: 2019-09-05 Inventor: Park, Sangjine   Cho byung kwon   Jeong, Jihoon   Kim, Youngtak   Ko, Yongsun   Jeon, Seulgee   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/02 Abstract: A supercritical drying apparatus and a method of drying a substrate, the apparatus including a drying chamber configured to receive a supercritical fluid and to dry a substrate; a chuck in the drying chamber, the chuck being configured to receive the substrate; and a particle remover in the drying chamber, the particle remover being configured to remove dry particles from the substrate by heating the substrate with radiant heat.
2
US10818522B2
Process chamber for a supercritical process and apparatus for treating substrates having the same
Publication/Patent Number: US10818522B2 Publication Date: 2020-10-27 Application Number: 15/978,303 Filing Date: 2018-05-14 Inventor: Park, Sang-jine   Cho byung kwon   Cho, Yong-jhin   Ko, Yong-sun   Gil, Yeon-jin   Lee, Kwang-wook   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/302 Abstract: Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.
3
KR20190034010A
Process chamber for a supercritical process and apparatus for treating substrates having the same
Publication/Patent Number: KR20190034010A Publication Date: 2019-04-01 Application Number: 20170122848 Filing Date: 2017-09-22 Inventor: Cho, Yong Jhin   Cho, Byung Kwon   Gil, Yeon Jin   Lee, Kwang Wook   Ko, Yong Sun   Park, Sang Jine   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/67 Abstract: Provided are a supercritical chamber and a substrate processing apparatus having the same. The supercritical chamber includes: a body having a body frame having a protrusion part and a recess and an inner vessel covering the protrusion part, detachably fixed to the body frame so as to be inserted into the recess, and providing a chamber space in the recess; and a cover having a flat-shaped cover frame and an inner cover detachably fixed to the cover frame, coupling to the body so that the inner cover and the inner vessel come in surface-contact with each other in the protrusion part, and limiting the chamber space. The present invention can simply prevent process faulty caused by abrasion of the contact surface by replacing the inner vessel and the inner cover when abrasion of a contact surface is generated in a coupling surface of the body and the cover.
4
KR20190051654A
method for treating substrate
Publication/Patent Number: KR20190051654A Publication Date: 2019-05-15 Application Number: 20170147527 Filing Date: 2017-11-07 Inventor: Cho, Yong Jhin   Lee, Kuntack   Cha, Ji Hoon   Cho, Byung Kwon   Gil, Yeonjin   Park, Sangjine   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/687 Abstract: The present invention discloses a substrate processing apparatus. The apparatus includes: a lower housing; an upper housing covering the lower housing; and a chuck provided between the upper housing and the lower housing and receiving a substrate. The upper housing can have a gap of 1.5 mm to 5.5 mm from the substrate on the chuck.
5
US10192973B2
Methods of forming semiconductor devices including trench walls having multiple slopes
Publication/Patent Number: US10192973B2 Publication Date: 2019-01-29 Application Number: 15/239,200 Filing Date: 2016-08-17 Inventor: Park, Sang-jine   Yoon, Bo-un   Jeon, Ha-young   Cho byung kwon   Han, Jeong-nam   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L29/66 Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
6
US2019096712A1
PROCESS CHAMBER FOR A SUPERCRITICAL PROCESS AND APPARATUS FOR TREATING SUBSTRATES HAVING THE SAME
Publication/Patent Number: US2019096712A1 Publication Date: 2019-03-28 Application Number: 15/978,303 Filing Date: 2018-05-14 Inventor: Park, Sang-jine   Cho byung kwon   Cho, Yong-jhin   Ko, Yong-sun   Gil, Yeon-jin   Lee, Kwang-wook   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/67 Abstract: Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.
7
US201996712A1
PROCESS CHAMBER FOR A SUPERCRITICAL PROCESS AND APPARATUS FOR TREATING SUBSTRATES HAVING THE SAME
Publication/Patent Number: US201996712A1 Publication Date: 2019-03-28 Application Number: 20/181,597 Filing Date: 2018-05-14 Inventor: Lee, Kwang-wook   Cho byung kwon   Cho, Yong-jhin   Gil, Yeon-jin   Park, Sang-jine   Ko, Yong-sun   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/67 Abstract: Disclosed are a supercritical process chamber and an apparatus having the same. The process chamber includes a body frame having a protrusion protruding in an upward vertical direction from a first surface of the body frame and a recess defined by the protrusion and the first surface of the body frame; a cover frame; a buffer chamber arranged between the body frame and the cover frame; and a connector. The buffer chamber includes an inner vessel detachably coupled to the body frame providing a chamber space in the recess and an inner cover detachably coupled to the cover frame. The inner cover is in contact with a first surface of the inner vessel enclosing the chamber space from surroundings. The connector couples the body frame and the cover frame having the buffer chamber arranged therebetween such that the enclosed chamber space is transformed into a process space in which the supercritical process is performed.
8
US10186485B2
Planarized interlayer dielectric with air gap isolation
Publication/Patent Number: US10186485B2 Publication Date: 2019-01-22 Application Number: 15/897,465 Filing Date: 2018-02-15 Inventor: Nguyen, Vietha   You, Wookyung   Naoya, Inoue   Lee, Hak-sun   Cho byung kwon   Han, Songyi   Baek, Jongmin   Kang, Jiwon   Kim, Byunghee   Park, Young-ju   Ahn, Sanghoon   Yun, Jiwon   Lee, Naein   Cho, Youngwoo   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L23/48 Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
9
KR20180034319A
열반응팩유니트
Title (English): Thermal reaction mask
Publication/Patent Number: KR20180034319A Publication Date: 2018-04-04 Application Number: 20177034899 Filing Date: 2015-06-29 Inventor: Jo, Byung Chul   Cho, Byung Kwon   Cho, Byoung Gu   Assignee: HARVEST CHARM FOOD CO., LTD.   IPC: B65D77/04 Abstract: 본 발명은 반응액체와 반응물질의 반응에 의해 내용물을 냉각 또는 가열하는 열반응팩유니트에 관한 것으로서, 수용팩과; 상기 수용팩 내에 수용되는 반응물질과; 상기 반응물질과 접촉하여 열반응을 일으키는 반응액체를 상기 반응물질과 격리되도록 밀봉수용하여 상기 수용팩 내에 수용되며, 일측의 고정연부가 상기 수용팩의 지지연부에 결합되고, 상기 고정연부로부터 상호 절개간격을 두고 상기 고정연부에 가로방향을 따라 상호 상이한 절개길이만큼 절개된 한 쌍의 절개선에 의해 형성된 테어링스트랩을 갖는 반응액체주머니와; 상기 테어링스트랩에 연결되어 상기 테어링스트랩을 상기 고정연부로부터 멀어지는 테어링방향으로 당길 수 있는 테어링부재를 포함하는 것을 특징으로 한다. 본 발명에 의한 열반응유니트는 테어링부재에 의해 물주머니를 쉽게 찢을 수 있다.
10
US9984921B2
Semiconductor device and method of manufacturing the same
Publication/Patent Number: US9984921B2 Publication Date: 2018-05-29 Application Number: 15/802,724 Filing Date: 2017-11-03 Inventor: Lee, Na Ein   Kim, Byung Hee   Cho, Byung Kwon   You, Woo Kyung   Song, Myung Geun   Baek, Jong Min   Ahn, Sang Hoon   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L23/528 Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
11
KR20180134179A
Substrate processing apparatus and apparatus for manufacturing integrated circuit device
Publication/Patent Number: KR20180134179A Publication Date: 2018-12-18 Application Number: 20170071729 Filing Date: 2017-06-08 Inventor: Gil, Yeon Jin   Jeong, Ji Hoon   Cho, Byung Kwon   Ko, Yong Sun   Park, Sang Jine   Kim, Young Hoo   Cho, Yong Jhin   Lee, Kun Tack   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/687 Abstract: Provided is a substrate processing apparatus which comprises: a vessel providing a processing space for processing a substrate; a substrate support supporting the substrate loaded in the processing space; and a barrier arranged between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.
12
US2018053685A1
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2018053685A1 Publication Date: 2018-02-22 Application Number: 15/802,724 Filing Date: 2017-11-03 Inventor: Ahn, Sang Hoon   Baek, Jong Min   Song, Myung Geun   You, Woo Kyung   Cho, Byung Kwon   Kim, Byung Hee   Lee, Na Ein   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/311 Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.
13
DE102018102592A1
Substratbearbeitungsvorrichtung und Vorrichtung zum Herstellen einer integrierten Schaltungsvorrichtung
Publication/Patent Number: DE102018102592A1 Publication Date: 2018-12-13 Application Number: 102018102592 Filing Date: 2018-02-06 Inventor: Jeong, Ji-hoon   Lee, Kun-tack   Ko, Yong-sun   Cho byung kwon   Kim, Young-hoo   Park, Sang-jine   Cho, Yong-jhin   Gil, Yeon-jin   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/67 Abstract: Eine Substratbearbeitungsvorrichtung (100) weist einen Behälter (110) auf, welcher einen Bearbeitungsraum (PS) zum Bearbeiten eines Substrats (W) vorsieht, eine Substratabstützung (130), welche das Substrat (W), welches in den Bearbeitungsraum (PS) geladen ist, abstützt, und eine Barriere (150) zwischen einer Seitenwand des Behälters (110) und der Substratabstützung (130) und einen Rand des Substrats (W), welches durch die Substratabstützung (130) abgestützt ist, umschließend.
14
WO2018004018A1
LIGHT-EMITTING DEVICE PACKAGE
Publication/Patent Number: WO2018004018A1 Publication Date: 2018-01-04 Application Number: 2016006836 Filing Date: 2016-06-27 Inventor: Jang, Jae-young   Cho byung kwon   Cho, Byoung-gu   Min, Jae-sik   Jo, Byung-chul   Lee, Jae-yeop   Assignee: LIGHTIZER KOREA CO., LTD   IPC: H01L33/48 Abstract: The present invention provides a light-emitting device package comprising: a light-emitting diode device for providing light of a wavelength in a predetermined region; a circuit board disposed at the lower surface of the light-emitting diode device so as to be electrically connected to the light-emitting diode device; a first phosphor layer formed in a cap shape so as to be disposed to encompass the side surfaces and the upper surface of the light-emitting diode device
15
US2018358242A1
Substrate Processing Apparatus and Apparatus for Manufacturing Integrated Circuit Device
Publication/Patent Number: US2018358242A1 Publication Date: 2018-12-13 Application Number: 15/827,144 Filing Date: 2017-11-30 Inventor: Kim, Young-hoo   Park, Sang-jine   Cho, Yong-jhin   Gil, Yeon-jin   Jeong, Ji-hoon   Cho byung kwon   Ko, Yong-sun   Lee, Kun-tack   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/67 Abstract: A substrate processing apparatus includes a vessel providing a processing space for processing a substrate, a substrate support supporting the substrate loaded in the processing space, and a barrier between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.
16
JP2018207103A
SUBSTRATE PROCESSING APPARATUS AND APPARATUS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE
Publication/Patent Number: JP2018207103A Publication Date: 2018-12-27 Application Number: 2018098876 Filing Date: 2018-05-23 Inventor: Cho byung kwon   Cho, Yong-jhin   Jeong, Ji-hoon   Park, Sang-jine   Ri, Kontaku   Gil, Yeon-jin   Kim, Younghoo   Ko, Yong-sun   Assignee: SAMSUNG ELECTRONICS CO LTD   IPC: H01L21/304 Abstract: To provide: a substrate processing apparatus capable of preventing defects from being generated in a substrate due to particles in a vessel during a drying process for the substrate; and an apparatus for manufacturing an integrated circuit device.SOLUTION: A substrate processing apparatus 100 includes a vessel 110 providing a processing space for processing a substrate W, a substrate support 130 supporting the substrate loaded in the processing space, and a barrier film 150 disposed between a side wall of the vessel and the substrate support and surrounding an edge of the substrate supported by the substrate support.SELECTED DRAWING: Figure 1A
17
US2018174977A1
PLANARIZED INTERLAYER DIELECTRIC WITH AIR GAP ISOLATION
Publication/Patent Number: US2018174977A1 Publication Date: 2018-06-21 Application Number: 15/897,465 Filing Date: 2018-02-15 Inventor: Cho, Youngwoo   Lee, Naein   Yun, Jiwon   Ahn, Sanghoon   Park, Young-ju   Kim, Byunghee   Kang, Jiwon   Baek, Jongmin   Han, Songyi   Cho byung kwon   Lee, Hak-sun   Naoya, Inoue   You, Wookyung   Nguyen, Vietha   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L23/522 Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
18
US9929099B2
Planarized interlayer dielectric with air gap isolation
Publication/Patent Number: US9929099B2 Publication Date: 2018-03-27 Application Number: 15/357,299 Filing Date: 2016-11-21 Inventor: Nguyen, Vietha   You, Wookyung   Naoya, Inoue   Lee, Hak-sun   Cho byung kwon   Han, Songyi   Baek, Jongmin   Kang, Jiwon   Kim, Byunghee   Park, Young-ju   Ahn, Sanghoon   Yun, Jiwon   Lee, Naein   Cho, Youngwoo   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L23/522 Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.
19
KR101746709B1
Methods of fabricating a semiconductor device including metal gate electrodes
Publication/Patent Number: KR101746709B1 Publication Date: 2017-06-14 Application Number: 20100117666 Filing Date: 2010-11-24 Inventor: Yoon, Bo Un   Choi, Suk Hun   Cho, Byung Kwon   Baek, Jae Jik   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/28 Abstract: PURPOSE: A manufacturing method of a semiconductor device which includes metal gate electrodes is provided to completely eliminate an uppermost metal film arranged within a first region using a patterned planarization film as an etching mask
20
WO2017002984A1
THERMAL REACTION PACK UNIT
Publication/Patent Number: WO2017002984A1 Publication Date: 2017-01-05 Application Number: 2015006623 Filing Date: 2015-06-29 Inventor: Cho, Byoung-gu   Cho byung kwon   Jo, Byung-chul   Assignee: HARVEST CHARMFOODS CO., LTD.   IPC: A47J36/24 Abstract: The present invention relates to a thermal reaction pack unit for cooling or heating contents by means of a reaction of a reaction liquid and a reactant
Total 6 pages