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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
EP3772103A1
METHODS OF FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES AND APPARATUS INCLUDING THE SAME
Publication/Patent Number: EP3772103A1 Publication Date: 2021-02-03 Application Number: 20188770.0 Filing Date: 2020-07-30 Inventor: Choi, Yoonyoung   Lee, Byunghyun   Ku, Byeongjoo   Kim, Seungjin   Park, Sangjae   Bae, Jinwoo   Lee, Hangeol   Choi, Bowo   Hong, Hyunsil   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L27/108 Abstract: The present disclosure provides capacitor forming methods which may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.
2
US2021036101A1
METHODS OF FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES AND APPARATUS INCLUDING THE SAME
Publication/Patent Number: US2021036101A1 Publication Date: 2021-02-04 Application Number: 16/947,090 Filing Date: 2020-07-17 Inventor: Choi, Yoonyoung   Lee, Byunghyun   Ku, Byeongjoo   Kim, Seungjin   Park, Sangjae   Bae, Jinwoo   Lee, Hangeol   Choi, Bowo   Hong, Hyunsil   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L49/02 Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.
3
US2020365537A1
SEMICONDUCTOR DEVICES HAVING LANDING PADS
Publication/Patent Number: US2020365537A1 Publication Date: 2020-11-19 Application Number: 16/674,056 Filing Date: 2019-11-05 Inventor: Choi, Bowo   Kim, Youngtak   Park, Sangjine   Kim, Suji   Shin, Jaeuk   Lee, Hyunjung   Cheon, Jihun   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L23/00 Abstract: A semiconductor device includes a landing pad, a first insulating pattern in contact with a lower portion of a side surface of the landing pad, a pad oxide layer having a lateral portion disposed on a portion of an upper surface of the landing pad and a vertical portion in contact with an upper portion of the side surface of the landing pad, a second insulating pattern in contact with an upper surface of the first insulating pattern and covering the first insulating pattern and the pad oxide layer, and a lower electrode that vertically passes through the second insulating pattern and is in contact with a portion of the upper surface and an upper portion of a side surface of the landing pad.