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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US10943819B2
Semiconductor structure having a plurality of capped protrusions
Publication/Patent Number: US10943819B2 Publication Date: 2021-03-09 Application Number: 16/296,627 Filing Date: 2019-03-08 Inventor: Chuang ying cheng   Assignee: Nanya Technology Corporation   IPC: H01L29/06 Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a base, a plurality of islands, and an isolation layer. At least one of the plurality of islands includes a pillar extending from an upper surface of the base, a protrusion connected to the pillar, a capping layer disposed on the protrusion, and a passivation liner disposed on sidewalls of the protrusion and the capping layer. The isolation layer surrounds the islands.
2
US2020321240A1
METHOD FOR FORMING A SHALLOW TRENCH STRUCTURE
Publication/Patent Number: US2020321240A1 Publication Date: 2020-10-08 Application Number: 16/375,264 Filing Date: 2019-04-04 Inventor: Huang, Chihlin   Chuang, Ying Cheng   Assignee: Nanya Technology Corporation   IPC: H01L21/762 Abstract: This invention provides a method for forming a shallow trench structure, including providing a substrate, forming a patterned photoresist layer on the substrate, performing an etching process with the patterned photoresist layer as a mask to form a shallow trench structure on the substrate, and applying plasma treatment unto the substrate with plasma produced from a mixture of CF4 and O2. Repeating the etching process and the plasma treatment until a shallow trench structure with a predetermined aspect ratio is obtained.
3
US2020203221A1
SEMICONDUCTOR STRUCTURE AND METHOD OF PROCESSING THE SAME
Publication/Patent Number: US2020203221A1 Publication Date: 2020-06-25 Application Number: 16/296,627 Filing Date: 2019-03-08 Inventor: Chuang ying cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a base, a plurality of islands, and an isolation layer. At least one of the plurality of islands includes a pillar extending from an upper surface of the base, a protrusion connected to the pillar, a capping layer disposed on the protrusion, and a passivation liner disposed on sidewalls of the protrusion and the capping layer. The isolation layer surrounds the islands.
4
US9659886B2
Method of fabricating semiconductor device having voids between top metal layers of metal interconnects
Publication/Patent Number: US9659886B2 Publication Date: 2017-05-23 Application Number: 15/193,117 Filing Date: 2016-06-27 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay, Chao-wen   Wu, Hung-mo   Chuang ying cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/528 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
5
TWI532136B
Semiconductor device and method of fabricating the same
Publication/Patent Number: TWI532136B Publication Date: 2016-05-01 Application Number: 102142675 Filing Date: 2013-11-22 Inventor: Wu, Hung Mo   Chuang, Ying Cheng   Wu, Ping Heng   Lay, Chao Wen   Lin, Chung Hsin   Assignee: Nanya Technology Corporation   IPC: H01L21/60 Abstract: The invention provides a semiconductor device including a substrate
6
US9418949B2
Semiconductor device having voids between top metal layers of metal interconnects
Publication/Patent Number: US9418949B2 Publication Date: 2016-08-16 Application Number: 14/028,554 Filing Date: 2013-09-17 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay, Chao-wen   Wu, Hung-mo   Chuang ying cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/528 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
7
US2016307859A1
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2016307859A1 Publication Date: 2016-10-20 Application Number: 15/193,117 Filing Date: 2016-06-27 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay, Chao-wen   Wu, Hung-mo   Chuang ying cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
8
TWI490924B
Semiconductor device and method for fabricating the same
Publication/Patent Number: TWI490924B Publication Date: 2015-07-01 Application Number: 102116521 Filing Date: 2013-05-09 Inventor: Chuang, Ying Cheng   Yang, Sheng Wei   Surthi, Shyam   Assignee: Nanya Technology Corporation   IPC: H01L21/22 Abstract: Provided is a method for fabricating a semiconductor device
9
US2015037961A1
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE
Publication/Patent Number: US2015037961A1 Publication Date: 2015-02-05 Application Number: 14/519,143 Filing Date: 2014-10-21 Inventor: Yang, Sheng-wei   Chuang ying cheng   Surthi, Shyam   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/765 Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
10
US9012303B2
Method for fabricating semiconductor device with vertical transistor structure
Publication/Patent Number: US9012303B2 Publication Date: 2015-04-21 Application Number: 14/519,143 Filing Date: 2014-10-21 Inventor: Yang, Sheng-wei   Chuang ying cheng   Surthi, Shyam   Assignee: Nanya Technology Corporation   IPC: H01L21/28 Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
11
TW201513284A
Semiconductor device and method of fabricating the same
Publication/Patent Number: TW201513284A Publication Date: 2015-04-01 Application Number: 102142675 Filing Date: 2013-11-22 Inventor: Wu, Hung Mo   Chuang, Ying Cheng   Wu, Ping Heng   Lay, Chao Wen   Lin, Chung Hsin   Assignee: Nanya Technology Corporation   IPC: H01L21/60 Abstract: The invention provides a semiconductor device including a substrate
12
US2015076698A1
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2015076698A1 Publication Date: 2015-03-19 Application Number: 14/028,554 Filing Date: 2013-09-17 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay, Chao-wen   Wu, Hung-mo   Chuang ying cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
13
TW201435985A
Semiconductor device and method for fabricating the same
Publication/Patent Number: TW201435985A Publication Date: 2014-09-16 Application Number: 102116521 Filing Date: 2013-05-09 Inventor: Chuang, Ying Cheng   Yang, Sheng Wei   Surthi, Shyam   Assignee: Nanya Technology Corporation   IPC: H01L21/22 Abstract: Provided is a method for fabricating a semiconductor device
14
US8901631B2
Vertical transistor in semiconductor device and method for fabricating the same
Publication/Patent Number: US8901631B2 Publication Date: 2014-12-02 Application Number: 20/131,379 Filing Date: 2013-03-11 Inventor: Surthi, Shyam   Chuang ying cheng   Yang, Sheng-wei   Assignee: Nanya Technology Corporation   Surthi, Shyam   Chuang ying cheng   Yang, Sheng-Wei   IPC: H01L21/765 Abstract: Provided is a method for fabricating a semiconductor device
15
US2014252532A1
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Publication/Patent Number: US2014252532A1 Publication Date: 2014-09-11 Application Number: 13/792,231 Filing Date: 2013-03-11 Inventor: Yang, Sheng-wei   Chuang ying cheng   Surthi, Shyam   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L29/06 Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
16
TWI424548B
Memory device and method of fabricating the same
Publication/Patent Number: TWI424548B Publication Date: 2014-01-21 Application Number: 100108227 Filing Date: 2011-03-11 Inventor: Chang, Ming Cheng   Chuang, Ying Cheng   Tsai, Hung Ming   Yang, Sheng Wei   Hsu, Ping Cheng   Assignee: Nanya Technology Corporation   IPC: H01L21/822 Abstract: A memory device includes a mesa structure and a word line. The mesa structure
17
TWI434400B
Memory device and method of fabricating the same
Publication/Patent Number: TWI434400B Publication Date: 2014-04-11 Application Number: 100112923 Filing Date: 2011-04-14 Inventor: Chang, Ming Cheng   Chuang, Ying Cheng   Tsai, Hung Ming   Yang, Sheng Wei   Hsu, Ping Cheng   Assignee: Nanya Technology Corporation   IPC: H01L21/8242 Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction
18
US8647988B2
Memory device and method of fabricating the same
Publication/Patent Number: US8647988B2 Publication Date: 2014-02-11 Application Number: 13/784,346 Filing Date: 2013-03-04 Inventor: Chuang, Ying Cheng   Hsu, Ping Cheng   Yang, Sheng Wei   Chang, Ming Cheng   Tsai, Hung Ming   Assignee: Nanya Technology Corporation   IPC: H01L21/311 Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
19
US8658538B2
Method of fabricating memory device
Publication/Patent Number: US8658538B2 Publication Date: 2014-02-25 Application Number: 13/788,497 Filing Date: 2013-03-07 Inventor: Chuang, Ying Cheng   Hsu, Ping Cheng   Yang, Sheng Wei   Chang, Ming Cheng   Tsai, Hung Ming   Assignee: Nanya Technology Corporation   IPC: H01L21/311 Abstract: A method of fabricating a memory device includes forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks.
20
US8415728B2
Memory device and method of fabricating the same
Publication/Patent Number: US8415728B2 Publication Date: 2013-04-09 Application Number: 12/945,423 Filing Date: 2010-11-12 Inventor: Chuang, Ying Cheng   Hsu, Ping Cheng   Yang, Sheng Wei   Chang, Ming Cheng   Tsai, Hung Ming   Assignee: Nanya Technology Corp.   IPC: H01L27/108 Abstract: A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.
Total 7 pages