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1
EP3780584A1
IMAGING ELEMENT AND ELECTRONIC DEVICE
Publication/Patent Number: EP3780584A1 Publication Date: 2021-02-17 Application Number: 19786059.6 Filing Date: 2019-04-03 Inventor: Etou, Shinichirou   Ikeda, Yusuke   Assignee: Sony Semiconductor Solutions Corporation   IPC: H04N5/378 Abstract: An imaging element according to a first aspect includes: a successive approximation resistor type analog-digital converter that converts an analog signal output from a pixel including a photoelectric conversion part into a digital signal, in which the successive approximation resistor type analog-digital converter has a preamplifier having a band limiting function. An imaging element according to a second aspect includes a DAC in which the successive approximation resistor type analog-digital converter uses a capacitance element to convert a digital value after AD conversion to an analog value, and sets the analog value to a comparison reference for comparison with an analog input voltage. Then, the DAC includes one of lower-bit capacitance elements including a plurality of capacitance elements, and after performing AD conversion for all bits, each of the plurality of capacitance elements is selectively applied with at least a first reference voltage to a fourth reference voltage, so that re-AD conversion is performed for lower bits.
2
US2021006255A1
PHASE-LOCKED LOOP
Publication/Patent Number: US2021006255A1 Publication Date: 2021-01-07 Application Number: 16/976,670 Filing Date: 2019-02-15 Inventor: Arisaka, Naoya   Fujiwara, Tetsuya   Etou, Shinichirou   Assignee: Sony Semiconductor Solutions Corporation   IPC: H03L7/089 Abstract: The present technology relates to a phase-locked loop that allows a reduction in power consumption. A SAR-ADC that includes two capacitors and outputs a result of comparison between voltages generated from the two capacitors, a current source that charges the two capacitors with current, a first switch that is disposed between one of the two capacitors and the current source and is provided with a phase difference between a first clock of a reference frequency and a second clock having a higher frequency than the first clock, and a second switch that is disposed between another of the two capacitors and the current source and is provided with the second clock are included. The present disclosure can be applied, for example, to a wireless communication device.
3
EP3761509A1
PHASE-LOCKED LOOP CIRCUIT
Publication/Patent Number: EP3761509A1 Publication Date: 2021-01-06 Application Number: 19761589.1 Filing Date: 2019-02-15 Inventor: Arisaka, Naoya   Fujiwara, Tetsuya   Etou, Shinichirou   Assignee: Sony Semiconductor Solutions Corporation   IPC: H03K5/26 Abstract: The present technology relates to a phase-locked loop that allows a reduction in power consumption. A SAR-ADC that includes two capacitors and outputs a result of comparison between voltages generated from the two capacitors, a current source that charges the two capacitors with current, a first switch that is disposed between one of the two capacitors and the current source and is provided with a phase difference between a first clock of a reference frequency and a second clock having a higher frequency than the first clock, and a second switch that is disposed between another of the two capacitors and the current source and is provided with the second clock are included. The present disclosure can be applied, for example, to a wireless communication device.
4
US2020343901A1
SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
Publication/Patent Number: US2020343901A1 Publication Date: 2020-10-29 Application Number: 16/959,775 Filing Date: 2018-12-18 Inventor: Etou, Shinichirou   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03M1/46 Abstract: A first successive approximation register analog-to-digital converter according an embodiment of the present disclosure includes an N-bit (N represents an integer greater than or equal to 5) capacitive digital-to-analog converter including a plurality of capacitive elements. A plurality of first capacitive elements of the plurality of capacitive elements is capacitive elements that have total capacity corresponding to total capacity of a plurality of the capacitive elements corresponding to a whole or a portion of first to (N−1)-th bits, and do not correspond to the first to (N−1)-th bits.
5
US2020412994A1
IMAGING ELEMENT AND ELECTRONIC DEVICE
Publication/Patent Number: US2020412994A1 Publication Date: 2020-12-31 Application Number: 16/977,026 Filing Date: 2019-04-03 Inventor: Etou, Shinichirou   Ikeda, Yusuke   Assignee: Sony Semiconductor Solutions Corporation   IPC: H04N5/378 Abstract: An imaging element according to a first aspect includes: a successive approximation resistor type analog-digital converter that converts an analog signal output from a pixel including a photoelectric conversion part into a digital signal, in which the successive approximation resistor type analog-digital converter has a preamplifier having a band limiting function. An imaging element according to a second aspect includes a DAC in which the successive approximation resistor type analog-digital converter uses a capacitance element to convert a digital value after AD conversion to an analog value, and sets the analog value to a comparison reference for comparison with an analog input voltage. Then, the DAC includes one of lower-bit capacitance elements including a plurality of capacitance elements, and after performing AD conversion for all bits, each of the plurality of capacitance elements is selectively applied with at least a first reference voltage to a fourth reference voltage, so that re-AD conversion is performed for lower bits.
6
US2020366298A1
TIME-TO-DIGITAL CONVERTER AND PHASE LOCKED LOOP
Publication/Patent Number: US2020366298A1 Publication Date: 2020-11-19 Application Number: 16/961,383 Filing Date: 2018-10-15 Inventor: Etou, Shinichirou   Fujiwara, Tetsuya   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03L7/089 Abstract: Power consumption of a time-to-digital converter (TDC) used in a phase locked loop (ADPLL) is suppressed. The time-to-digital converter includes an analog-to-digital converter and a current source circuit. The analog-to-digital converter includes a predetermined charge capacitor. The current source circuit supplies a charge current that charges the charge capacitor of the analog-to-digital converter with a charge. The charge current supplied by the current source circuit is supplied so that a charge voltage at the time of charging the charge capacitor of the analog-to-digital converter with the charge current has a constant gradient with respect to a charge time.
7
US10686460B2
Analog-to-digital converter, electronic device, and method for controlling analog-to-digital converter
Publication/Patent Number: US10686460B2 Publication Date: 2020-06-16 Application Number: 16/325,146 Filing Date: 2017-07-07 Inventor: Iguchi, Taiki   Etou, Shinichirou   Ueno, Yosuke   Hirono, Daisuke   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03M1/00 Abstract: The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.
8
US2020366863A1
SOLID-STATE IMAGING ELEMENT, IMAGING APPARATUS, AND CONTROL METHOD OF SOLID-STATE IMAGING ELEMENT
Publication/Patent Number: US2020366863A1 Publication Date: 2020-11-19 Application Number: 16/761,224 Filing Date: 2018-09-21 Inventor: Etou, Shinichirou   Ueno, Yosuke   Hino, Yasufumi   Tomita, Kazutoshi   Assignee: Sony Semiconductor Solutions Corporation   IPC: H04N5/3745 Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.
9
WO2019138804A1
SEQUENTIAL COMPARISON ANALOG DIGITAL CONVERTER
Publication/Patent Number: WO2019138804A1 Publication Date: 2019-07-18 Application Number: 2018046584 Filing Date: 2018-12-18 Inventor: Etou, Shinichirou   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03M1/38 Abstract: This first sequential comparison analog digital converter of an embodiment of the present disclosure comprises an N-bit (N is an integer of 5 or greater) capacity digital analog converter configured including a plurality of capacitative elements. A plurality of first capacitative elements among the plurality of capacitative elements have a total capacity corresponding to the total capacity of the plurality of capacitative elements that are associated with some or all of the 1st to N–1th bits, the plurality of first capacitative elements not being associated with the 1st to N–1th bits.
10
WO2019146177A1
TIME-TO-DIGITAL CONVERTING CIRCUIT AND PHASE-LOCKED LOOP
Publication/Patent Number: WO2019146177A1 Publication Date: 2019-08-01 Application Number: 2018038313 Filing Date: 2018-10-15 Inventor: Etou, Shinichirou   Fujiwara, Tetsuya   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03K5/26 Abstract: According to the present invention, power consumption is suppressed in a time-to-digital converting circuit (TDC) used in a phase-locked loop. The time-to-digital converting circuit is provided with an analog-to-digital converting circuit and a current source circuit. The analog-to-digital converting circuit is provided with a prescribed charge capacitor. The current source circuit supplies a charge current that charges an electric charge to the charge capacitor of the analog-to-digital converting circuit. The charge current is supplied by the current source circuit such that a charged voltage has a constant slope over a charge time while the charge capacitor of the analog-to-digital converting circuit is charged by the charge current,.
11
WO2019198586A1
IMAGING ELEMENT AND ELECTRONIC DEVICE
Publication/Patent Number: WO2019198586A1 Publication Date: 2019-10-17 Application Number: 2019014752 Filing Date: 2019-04-03 Inventor: Ikeda, Yusuke   Etou, Shinichirou   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H04N5/378 Abstract: An imaging element according to a first aspect is provided with a successive approximation type analog-digital converter which converts an analog signal outputted from a pixel including a photoelectric conversion unit into a digital signal, and the successive approximation type analog-digital converter comprises a preamplifier having a band limiting function. In an imaging element according to a second aspect, a successive approximation type analog-digital converter comprises a DAC which converts an AD converted digital value into an analog value using a capacitive element, and uses the analog value as a comparison criterion for comparison with analog input voltage. In the DAC, one of lower bit capacitive elements comprises a plurality of capacitive elements, and by at least first reference voltage to fourth reference voltage being selectively applied to each of the plurality of capacitive elements after AD conversion is performed on all bits, AD conversion is performed again on lower bits.
12
WO2019092994A1
SOLID-STATE IMAGING APPARATUS
Publication/Patent Number: WO2019092994A1 Publication Date: 2019-05-16 Application Number: 2018035166 Filing Date: 2018-09-21 Inventor: Hino, Yasufumi   Ueno, Yosuke   Etou, Shinichirou   Tomita, Kazutoshi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03M1/46 Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.
13
WO2019167670A1
PHASE-LOCKED LOOP CIRCUIT
Publication/Patent Number: WO2019167670A1 Publication Date: 2019-09-06 Application Number: 2019005554 Filing Date: 2019-02-15 Inventor: Fujiwara, Tetsuya   Etou, Shinichirou   Arisaka, Naoya   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03K5/26 Abstract: The present art relates to a phase-locked loop circuit that enables power consumption to be reduced. The phase-locked loop circuit comprises: an SAR-ADC that includes two capacitors and outputs a comparison result of voltages occurring across the two capacitors; an electric current source that charges the two capacitors with electric current; a first switch that is arranged between the electric current source and one of the two capacitors and supplied with a phase difference between a first clock having a reference frequency and a second clock having a frequency higher than the first clock; and a second switch that is arranged between the electric current source and the other of the two capacitors and supplied with the second clock. The present disclosure can be applied, for example, to a wireless communication device.
14
US2019190526A1
ANALOG-TO-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING ANALOG-TO-DIGITAL CONVERTER
Publication/Patent Number: US2019190526A1 Publication Date: 2019-06-20 Application Number: 16/325,146 Filing Date: 2017-07-07 Inventor: Iguchi, Taiki   Etou, Shinichirou   Ueno, Yosuke   Hirono, Daisuke   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03M1/00 Abstract: The present invention aims to reduce power consumption in an ADC that performs AD conversion of a single-ended signal. A pair of sampling capacitors samples the single-ended signal. After the single-ended signal has been sampled, the connection control unit performs positive-side connection control of connecting both ends of one of the pair of sampling capacitors across a positive-side signal line and a predetermined ground potential and performs negative-side connection control of connecting both ends of the other of the pair of sampling capacitors across a negative-side signal line and the predetermined ground potential. A conversion unit converts a differential signals from the positive-side signal line and the negative-side signal line that have respectively undergone the positive-side connection control and the negative-side connection control into a digital signal.
15
WO2018047457A1
ANALOG-DIGITAL CONVERTER, ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING ANALOG-DIGITAL CONVERTER
Publication/Patent Number: WO2018047457A1 Publication Date: 2018-03-15 Application Number: 2017024944 Filing Date: 2017-07-07 Inventor: Hirono, Daisuke   Ueno, Yosuke   Iguchi, Taiki   Etou, Shinichirou   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H03F3/70 Abstract: Power consumption is reduced in an ADC that performs AD conversion of single end signals. A pair of sampling capacitors samples the single end signals. When the single end signal is sampled, a connection control unit performs positive side connection control for connecting both ends of one of the pair of sampling capacitors between a positive side signal line and a prescribed reference potential, and negative side connection control for connecting both ends of the other of the pair of sampling capacitors between a negative side signal line and the prescribed reference potential. A conversion unit converts to digital signals the differential signals from the positive side signal line and the negative side signal line for which the positive side connection control and the negative side connection control were performed.
16
WO2017010136A1
PORTABLE TERMINAL DEVICE AUTHENTICATING SYSTEM
Publication/Patent Number: WO2017010136A1 Publication Date: 2017-01-19 Application Number: 2016062335 Filing Date: 2016-04-19 Inventor: Kuriyama, Kazuyuki   Etou, Shinichirou   Matsuda, Takayuki   Assignee: HONDA LOCK MFG. CO., LTD.   IPC: B60R25/24 Abstract: In this portable terminal device authenticating system: an on-board device transmits a request signal including a plurality of authentication signals having different signal intensities; a portable terminal device receives the request signal
17
US8487801B2
Analog-to-digital converter and signal processing system
Publication/Patent Number: US8487801B2 Publication Date: 2013-07-16 Application Number: 13/435,178 Filing Date: 2012-03-30 Inventor: Etou, Shinichirou   Shimizu, Yasuhide   Kudou, Kouhei   Yamashita, Yukitoshi   Assignee: Sony Corporation   IPC: H03M1/12 Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N−m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.
18
US8497794B2
Analog-digital converter and signal processing system
Publication/Patent Number: US8497794B2 Publication Date: 2013-07-30 Application Number: 13/435,173 Filing Date: 2012-03-30 Inventor: Etou, Shinichirou   Shimizu, Yasuhide   Kudou, Kouhei   Yamashita, Yukitoshi   Assignee: Sony Corporation   IPC: H03M1/38 Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.
19
US2012268302A1
ANALOG-DIGITAL CONVERTER AND SIGNAL PROCESSING SYSTEM
Publication/Patent Number: US2012268302A1 Publication Date: 2012-10-25 Application Number: 13/435,173 Filing Date: 2012-03-30 Inventor: Etou, Shinichirou   Shimizu, Yasuhide   Kudou, Kouhei   Yamashita, Yukitoshi   Assignee: Sony Corporation   IPC: H03M1/38 Abstract: An AD converter includes: AD conversion stages configured to generate digital data having a value corresponding to a relationship between two analog signals being input and amplifying two analog residual signals with a first amplifier and a second amplifier with gain to be controlled to output the signals; and a gain control part configured to control gain of the first amplifier and the second amplifier on the basis of a monitoring result of the output signals of the first amplifier and the second amplifier. The first amplifier and the second amplifier are formed of open-loop amplifiers, and the gain control part takes out amplitude information of the output signals of the first amplifier and the second amplifier in at least one of the AD conversion stages and performs gain control so that amplitude of the analog signals being output from the stage converges on setting amplitude being set.
20
US2012268300A1
ANALOG-TO-DIGITAL CONVERTER AND SIGNAL PROCESSING SYSTEM
Publication/Patent Number: US2012268300A1 Publication Date: 2012-10-25 Application Number: 13/435,178 Filing Date: 2012-03-30 Inventor: Etou, Shinichirou   Shimizu, Yasuhide   Kudou, Kouhei   Yamashita, Yukitoshi   Assignee: Sony Corporation   IPC: H03M1/12 Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N−m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.
Total 2 pages