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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
EP3329313B1
LENS ATTACHED SUBSTRATE, LAYERED LENS STRUCTURE, CAMERA MODULE, MANUFACTURING APPARATUS, AND MANUFACTURING METHOD
Publication/Patent Number: EP3329313B1 Publication Date: 2021-02-17 Application Number: 16751016.3 Filing Date: 2016-07-15 Inventor: Moriya, Yusuke   Iwasaki, Masanori   Oinoue, Takashi   Hagimoto, Yoshiya   Matsugai, Hiroyasu   Itou, Hiroyuki   Saito, Suguru   Ohshima, Keiji   Fujii, Nobutoshi   Tazawa, Hiroshi   Shiraiwa, Toshiaki   Ishida, Minoru   Assignee: Sony Semiconductor Solutions Corporation   IPC: G02B13/00
2
US2020127039A1
LIGHT-RECEIVING DEVICE, METHOD OF MANUFACTURING LIGHT RECEIVING DEVICE, IMAGING DEVICE, AND ELECTRONIC APPARATUS
Publication/Patent Number: US2020127039A1 Publication Date: 2020-04-23 Application Number: 16/477,969 Filing Date: 2017-12-19 Inventor: Saito, Suguru   Fujii, Nobutoshi   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/146 Abstract: There is provided a light-receiving device including: a plurality of photoelectric conversion layers including a first photoelectric conversion layer and a second photoelectric conversion layer disposed in respective regions that are different in a planar view; an insulating film that separates the plurality of photoelectric conversion layers from one another; a first inorganic semiconductor material included in the first photoelectric conversion layer; and a second inorganic semiconductor material included in the second photoelectric conversion layer, and different from the first inorganic semiconductor material.
3
EP2717300B1
SEMICONDUCTOR DEVICE
Publication/Patent Number: EP2717300B1 Publication Date: 2020-03-18 Application Number: 12790013.2 Filing Date: 2012-05-16 Inventor: Fujii, Nobutoshi   Kagawa, Yoshihisa   Assignee: Sony Corporation   IPC: H01L23/522
4
US202020733A1
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS
Publication/Patent Number: US202020733A1 Publication Date: 2020-01-16 Application Number: 20/181,649 Filing Date: 2018-02-15 Inventor: Hagimoto, Yoshiya   Fujii, Nobutoshi   Assignee: Sony Semiconductor Solutions Corporation   IPC: H01L27/146 Abstract: [Solution] Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer is provided with a porous film, the porous film including a porous material, in at least a partial region between an electrically-conductive material and a sidewall of a through hole filled with the electrically-conductive material, the electrically-conductive material constituting the electrode and the via.
5
US2020020733A1
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS
Publication/Patent Number: US2020020733A1 Publication Date: 2020-01-16 Application Number: 16/497,106 Filing Date: 2018-02-15 Inventor: Fujii, Nobutoshi   Hagimoto, Yoshiya   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/146 Abstract: [Object] To enable reliability to be further improved in a semiconductor device. [Solution] Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer is provided with a porous film, the porous film including a porous material, in at least a partial region between an electrically-conductive material and a sidewall of a through hole filled with the electrically-conductive material, the electrically-conductive material constituting the electrode and the via.
6
US10707258B2
Semiconductor device with multiple substrates electrically connected through an insulating film
Publication/Patent Number: US10707258B2 Publication Date: 2020-07-07 Application Number: 15/987,278 Filing Date: 2018-05-23 Inventor: Fujii, Nobutoshi   Hagimoto, Yoshiya   Aoyagi, Kenichi   Kagawa, Yoshihisa   Assignee: Sony Corporation   IPC: H01L27/146 Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
7
US10753551B2
Electronic component, electronic component mounting substrate, and electronic component mounting method to facilitate positional alignment between the electronic component and the mounting substrate
Publication/Patent Number: US10753551B2 Publication Date: 2020-08-25 Application Number: 15/554,872 Filing Date: 2016-01-27 Inventor: Hasegawa, Toshiaki   Aoyagi, Kenichi   Hagimoto, Yoshiya   Fujii, Nobutoshi   Assignee: Sony Semiconductor Solutions Corporation   IPC: H05K1/18 Abstract: An electronic component mounting substrate 10A is configured of an electronic component 20, and a mounting substrate 10 mounting the electronic component 20 thereon, in which concave parts 24 are formed on a mounting surface 23 of the electronic component 20 opposite to the mounting substrate 10, a connection part 39 is exposed at the bottom of the concave part 24, and electronic component attachment parts 12 provided on the mounting substrate 10 are soldered to the connection parts 39 provided in the electronic component 20.
8
US2020350198A1
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
Publication/Patent Number: US2020350198A1 Publication Date: 2020-11-05 Application Number: 16/959,723 Filing Date: 2018-12-28 Inventor: Saito, Suguru   Fujii, Nobutoshi   Haneda, Masaki   Nagahata, Kazunori   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L21/768 Abstract: The present technology relates to a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes. For example, the present technology can be applied to a semiconductor device in which wiring layers are stacked, and the like.
9
US2020035739A1
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
Publication/Patent Number: US2020035739A1 Publication Date: 2020-01-30 Application Number: 16/604,062 Filing Date: 2018-04-16 Inventor: Saito, Suguru   Fujii, Nobutoshi   Matsumoto, Ryosuke   Zaizen, Yoshifumi   Manda, Shuji   Maruyama, Shunsuke   Shimizu, Hideo   Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION   IPC: H01L27/146 Abstract: A semiconductor device including a device substrate and a readout circuit substrate. The device substrate includes a device region and a peripheral region. In the device region, a wiring layer and a first semiconductor layer including a compound semiconductor material are stacked. The peripheral region is disposed outside the device region. The readout circuit substrate faces the first semiconductor layer with the wiring layer in between, and is electrically coupled to the first semiconductor layer through the wiring layer. The peripheral region of the device substrate has a junction surface with the readout circuit substrate.
10
EP3614434A1
SEMICONDUCTOR ELEMENT, METHOD FOR PRODUCING SAME, AND ELECTRONIC DEVICE
Publication/Patent Number: EP3614434A1 Publication Date: 2020-02-26 Application Number: 18787243.7 Filing Date: 2018-04-16 Inventor: Saito, Suguru   Fujii, Nobutoshi   Matsumoto, Ryosuke   Zaizen, Yoshifumi   Manda, Shuji   Maruyama, Shunsuke   Shimizu, Hideo   Assignee: Sony Semiconductor Solutions Corporation   IPC: H01L27/146 Abstract: A semiconductor device including a device substrate and a readout circuit substrate. The device substrate includes a device region and a peripheral region. In the device region, a wiring layer and a first semiconductor layer including a compound semiconductor material are stacked. The peripheral region is disposed outside the device region. The readout circuit substrate faces the first semiconductor layer with the wiring layer in between, and is electrically coupled to the first semiconductor layer through the wiring layer. The peripheral region of the device substrate has a junction surface with the readout circuit substrate.
11
US10804313B2
Semiconductor device and solid-state imaging device
Publication/Patent Number: US10804313B2 Publication Date: 2020-10-13 Application Number: 16/001,278 Filing Date: 2018-06-06 Inventor: Kagawa, Yoshihisa   Fujii, Nobutoshi   Fukasawa, Masanaga   Kaneguchi, Tokihisa   Hagimoto, Yoshiya   Aoyagi, Kenichi   Mitsuhashi, Ikue   Assignee: Sony Corporation   IPC: H01L27/146 Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
12
US202035739A1
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS
Publication/Patent Number: US202035739A1 Publication Date: 2020-01-30 Application Number: 20/181,660 Filing Date: 2018-04-16 Inventor: Shimizu, Hideo   Fujii, Nobutoshi   Maruyama, Shunsuke   Zaizen, Yoshifumi   Matsumoto, Ryosuke   Manda, Shuji   Saito, Suguru   Assignee: Sony Semiconductor Solutions Corporation   IPC: H01L31/0304 Abstract: A semiconductor device including a device substrate and a readout circuit substrate. The device substrate includes a device region and a peripheral region. In the device region, a wiring layer and a first semiconductor layer including a compound semiconductor material are stacked. The peripheral region is disposed outside the device region. The readout circuit substrate faces the first semiconductor layer with the wiring layer in between, and is electrically coupled to the first semiconductor layer through the wiring layer. The peripheral region of the device substrate has a junction surface with the readout circuit substrate.
13
US10690814B2
Lens substrate, semiconductor device, and electronic apparatus
Publication/Patent Number: US10690814B2 Publication Date: 2020-06-23 Application Number: 15/747,302 Filing Date: 2016-07-19 Inventor: Shiraiwa, Toshiaki   Okamoto, Masaki   Matsugai, Hiroyasu   Itou, Hiroyuki   Saito, Suguru   Ohshima, Keiji   Fujii, Nobutoshi   Tazawa, Hiroshi   Ishida, Minoru   Assignee: Sony Semiconductor Solutions Corporation   IPC: G02B3/00 Abstract: Influence of chipping in case of dicing a plurality of stacked substrates is reduced. Provided is a semiconductor device where a substrate, in which a groove surrounding a pattern configured with a predetermined circuit or part is formed, is stacked. The present technology can be applied to, for example, a stacked lens structure where through-holes are formed in each substrate and lenses are disposed in inner sides of the through-holes, a camera module where a stacked lens structure and a light-receiving device are incorporated, a solid-state imaging device where a pixel substrate and a control substrate are stacked, and the like.