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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10540275B2
Memory controller, information processing system, and memory extension area management method
Publication/Patent Number: US10540275B2 Publication Date: 2020-01-21 Application Number: 15/523,763 Filing Date: 2015-10-08 Inventor: Okubo, Hideaki   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/00 Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable. To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the ...More ...Less
2 US10545804B2
Memory controller, memory system, and memory controller control method
Publication/Patent Number: US10545804B2 Publication Date: 2020-01-28 Application Number: 15/507,413 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F11/00 Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell. [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed ...More ...Less
3 US10310742B2
Memory controller, storage apparatus, information processing system, and method for controlling nonvolatile memory
Publication/Patent Number: US10310742B2 Publication Date: 2019-06-04 Application Number: 15/505,826 Filing Date: 2015-07-14 Inventor: Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/00 Abstract: The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile memory including the memory cell having an unstable state period after writing data. A verification unit performs verification by comparing read data which is read from the memory cell where the data is written on the basis of a result of the determination, with write data involved in the writing. A write control unit performs writing of the data and rewriting of the write data based on a result of the verification. The write reliability of a nonvolatile memory is improved by performing accurate verification of write data. In a memory controller of an information processing system, a determination unit determines whether a state of a memory cell after writing data is stable in a nonvolatile ...More ...Less
4 US2019056884A1
MEMORY CONTROLLER, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND MEMORY CONTROL METHOD
Publication/Patent Number: US2019056884A1 Publication Date: 2019-02-21 Application Number: 15/768,597 Filing Date: 2016-07-27 Inventor: Ishii, Ken   Iwaki, Hiroyuki   Nakanishi, Kenichi   Fujinami, Yasushi   Shinbashi, Tatsuo   Assignee: SONY CORPORATION   IPC: G06F3/06 Abstract: The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding units holds a write request with respect to each of a plurality of memory modules that require different write times from one another. The selection unit selects one of the plurality of write request holding units in accordance with memory state information indicating whether each of the plurality of memory modules is in a busy state, and causes outputting of the write request. The write time is to be shortened in a storage device using memories that require different write times from each other, such as nonvolatile memories. In a memory controller including a plurality of write request holding units and a selection unit, the write request holding ...More ...Less
5 EP3211536B1
MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY CONTROLLER CONTROL METHOD
Publication/Patent Number: EP3211536B1 Publication Date: 2019-09-04 Application Number: 15851846.4 Filing Date: 2015-07-22 Inventor: Shinbashi, Tatsuo   Tsutsui, Keiichi   Okubo, Hideaki   Sakai, Lui   Nakanishi, Kenichi   Fujinami, Yasushi   Assignee: Sony Corporation   IPC: G06F12/16
6 US10481971B2
Encoding device, memory controller, communication system, and encoding method
Publication/Patent Number: US10481971B2 Publication Date: 2019-11-19 Application Number: 15/736,079 Filing Date: 2016-04-15 Inventor: Shinbashi, Tatsuo   Nakanishi, Kenichi   Fujinami, Yasushi   Iwaki, Hiroyuki   Ishii, Ken   Okubo, Hideaki   Assignee: Sony Corporation   IPC: G06F11/10 Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity. A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in ...More ...Less