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1 | US2021111204A1 |
SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC EQUIPMENT
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Publication/Patent Number: US2021111204A1 | Publication Date: 2021-04-15 | Application Number: 16/496,773 | Filing Date: 2018-03-16 | Inventor： Hagimoto, Yoshiya | Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION | IPC: H01L27/146 | Abstract: The present technology relates to a semiconductor device, a solid-state imaging device, and electronic equipment, which are able to suppress increase of resistivity to a high level at a connection portion between an ESV and a wiring layer and to improve reliability of an electric connection using an ESV. The semiconductor device according to a first aspect of the present technology has a plurality of semiconductor substrates layered, and includes: a through electrode penetrating a silicon layer of the semiconductor substrates; a wiring layer formed inside the semiconductor substrates; and a through electrode reception part connected to the wiring layer, in which the through electrode has a width smaller than the through electrode reception part, and the through electrode is electrically connected to the wiring layer via the through electrode reception part. The present technology is applicable, for example, to a CMOS image sensor. | |||
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2 | EP3329313B1 |
LENS ATTACHED SUBSTRATE, LAYERED LENS STRUCTURE, CAMERA MODULE, MANUFACTURING APPARATUS, AND MANUFACTURING METHOD
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Publication/Patent Number: EP3329313B1 | Publication Date: 2021-02-17 | Application Number: 16751016.3 | Filing Date: 2016-07-15 | Inventor： Moriya, Yusuke Iwasaki, Masanori Oinoue, Takashi Hagimoto, Yoshiya Matsugai, Hiroyasu Itou, Hiroyuki Saito, Suguru Ohshima, Keiji Fujii, Nobutoshi Tazawa, Hiroshi Shiraiwa, Toshiaki Ishida, Minoru | Assignee: Sony Semiconductor Solutions Corporation | IPC: G02B13/00 | ||||
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3 | US202020733A1 |
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS
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Publication/Patent Number: US202020733A1 | Publication Date: 2020-01-16 | Application Number: 20/181,649 | Filing Date: 2018-02-15 | Inventor： Hagimoto, Yoshiya Fujii, Nobutoshi | Assignee: Sony Semiconductor Solutions Corporation | IPC: H01L27/146 | Abstract: [Solution] Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer is provided with a porous film, the porous film including a porous material, in at least a partial region between an electrically-conductive material and a sidewall of a through hole filled with the electrically-conductive material, the electrically-conductive material constituting the electrode and the via. | |||
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4 | US2020020733A1 |
SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS
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Publication/Patent Number: US2020020733A1 | Publication Date: 2020-01-16 | Application Number: 16/497,106 | Filing Date: 2018-02-15 | Inventor： Fujii, Nobutoshi Hagimoto, Yoshiya | Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION | IPC: H01L27/146 | Abstract: [Object] To enable reliability to be further improved in a semiconductor device. [Solution] Provided is a semiconductor device including a plurality of substrates that is stacked, each of the substrates including a semiconductor substrate and a multi-layered wiring layer stacked on the semiconductor substrate, the semiconductor substrate having a circuit with a predetermined function formed thereon. Bonding surfaces between at least two substrates among the plurality of substrates have an electrode junction structure in which electrodes formed on the respective bonding surfaces are joined in direct contact with each other, the electrode junction structure being a structure for electrical connection between the two substrates. In at least one of the two substrates, at least one of the electrode constituting the electrode junction structure or a via for connection of the electrode to a wiring line in the multi-layered wiring layer is provided with a porous film, the porous film including a porous material, in at least a partial region between an electrically-conductive material and a sidewall of a through hole filled with the electrically-conductive material, the electrically-conductive material constituting the electrode and the via. | |||
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5 | US10753551B2 |
Electronic component, electronic component mounting substrate, and electronic component mounting method to facilitate positional alignment between the electronic component and the mounting substrate
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Publication/Patent Number: US10753551B2 | Publication Date: 2020-08-25 | Application Number: 15/554,872 | Filing Date: 2016-01-27 | Inventor： Hasegawa, Toshiaki Aoyagi, Kenichi Hagimoto, Yoshiya Fujii, Nobutoshi | Assignee: Sony Semiconductor Solutions Corporation | IPC: H05K1/18 | Abstract: An electronic component mounting substrate 10A is configured of an electronic component 20, and a mounting substrate 10 mounting the electronic component 20 thereon, in which concave parts 24 are formed on a mounting surface 23 of the electronic component 20 opposite to the mounting substrate 10, a connection part 39 is exposed at the bottom of the concave part 24, and electronic component attachment parts 12 provided on the mounting substrate 10 are soldered to the connection parts 39 provided in the electronic component 20. | |||
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6 | US10707258B2 |
Semiconductor device with multiple substrates electrically connected through an insulating film
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Publication/Patent Number: US10707258B2 | Publication Date: 2020-07-07 | Application Number: 15/987,278 | Filing Date: 2018-05-23 | Inventor： Fujii, Nobutoshi Hagimoto, Yoshiya Aoyagi, Kenichi Kagawa, Yoshihisa | Assignee: Sony Corporation | IPC: H01L27/146 | Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other. | |||
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7 | US10699968B2 |
Semiconductor manufacturing apparatus
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Publication/Patent Number: US10699968B2 | Publication Date: 2020-06-30 | Application Number: 13/408,293 | Filing Date: 2012-02-29 | Inventor： Takeya, Yukari Iwamoto, Hayato Hagimoto, Yoshiya Motooka, Eizo | Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION | IPC: H01L21/66 | Abstract: A semiconductor manufacturing apparatus includes: a treatment chamber treating a treated film of a wafer using a desired chemical fluid; a film thickness measurement unit measuring an initial film thickness of the treated film before treatment and a final film thickness of the treated film after treatment; and a main body controlling unit calculating a treatment speed of the chemical fluid from the initial film thickness, the final film thickness, and a chemical fluid treatment time taken from the initial film thickness to the final film thickness to calculate a chemical fluid treatment time for a wafer to be treated next from the calculated treatment speed. | |||
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8 | US10804313B2 |
Semiconductor device and solid-state imaging device
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Publication/Patent Number: US10804313B2 | Publication Date: 2020-10-13 | Application Number: 16/001,278 | Filing Date: 2018-06-06 | Inventor： Kagawa, Yoshihisa Fujii, Nobutoshi Fukasawa, Masanaga Kaneguchi, Tokihisa Hagimoto, Yoshiya Aoyagi, Kenichi Mitsuhashi, Ikue | Assignee: Sony Corporation | IPC: H01L27/146 | Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device. | |||
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9 | US2020083262A1 |
SOLID-STATE IMAGE SENSING DEVICE AND ELECTRONIC DEVICE
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Publication/Patent Number: US2020083262A1 | Publication Date: 2020-03-12 | Application Number: 16/683,379 | Filing Date: 2019-11-14 | Inventor： Tayanaka, Hiroshi Akiyama, Kentaro Sakano, Yorito Oinoue, Takashi Hagimoto, Yoshiya Matsumura, Yusuke Sato, Naoyuki Miyanami, Yuki Ueda, Yoichi Matsumoto, Ryosuke | Assignee: SONY CORPORATION | IPC: H01L27/146 | Abstract: The present technology relates to a solid-state image sensing device and an electronic device for reducing noises. The solid-state image sensing device includes: a photoelectric conversion unit; a charge holding unit for holding charges transferred from the photoelectric conversion unit; a first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and a light blocking part including a first light blocking part and a second light blocking part, in which the first light blocking part is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit, and covers the second surface, and is formed with a first opening, and the second light blocking part surrounds the side surface of the photoelectric conversion unit. The present technology is applicable to solid-state image sensing devices of backside irradiation type, for example. | |||
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10 | US202049959A1 |
LENS ATTACHED SUBSTRATE, LAYERED LENS STRUCTURE, CAMERA MODULE, MANUFACTURING APPARATUS, AND MANUFACTURING METHOD
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Publication/Patent Number: US202049959A1 | Publication Date: 2020-02-13 | Application Number: 20/191,650 | Filing Date: 2019-07-10 | Inventor： Ishida, Minoru Iwasaki, Masanori Hagimoto, Yoshiya Shiraiwa, Toshiaki Itou, Hiroyuki Fujii, Nobutoshi Matsugai, Hiroyasu Moriya, Yusuke Tazawa, Hiroshi Oinoue, Takashi Saito, Suguru Ohshima, Keiji | Assignee: Sony Semiconductor Solutions Corporation | IPC: G02B27/00 | Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like. | |||
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11 | US2020049959A1 |
LENS ATTACHED SUBSTRATE, LAYERED LENS STRUCTURE, CAMERA MODULE, MANUFACTURING APPARATUS, AND MANUFACTURING METHOD
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Publication/Patent Number: US2020049959A1 | Publication Date: 2020-02-13 | Application Number: 16/507,984 | Filing Date: 2019-07-10 | Inventor： Moriya, Yusuke Iwasaki, Masanori Oinoue, Takashi Hagimoto, Yoshiya Matsugai, Hiroyasu Itou, Hiroyuki Saito, Suguru Ohshima, Keiji Fujii, Nobutoshi Tazawa, Hiroshi Shiraiwa, Toshiaki Ishida, Minoru | Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION | IPC: G02B13/00 | Abstract: The present technology relates to, for example, a lens attached substrate including a substrate which has a through-hole formed therein and a light shielding film formed on a side wall of the through-hole and a lens resin portion which is formed inside the through-hole of the substrate. The present technology can be applied to, for example, a lens attached substrate, a layered lens structure, a camera module, a manufacturing apparatus, a manufacturing method, an electronic device, a computer, a program, a storage medium, a system, and the like. |
