Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
EP2889901B1
Semiconductor device with through-substrate via and corresponding method
Publication/Patent Number: EP2889901B1 Publication Date: 2021-02-03 Application Number: 13199683.7 Filing Date: 2013-12-27 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Löffler, Bernhard   Holzhaider, Rainer   Assignee: ams AG   IPC: H01L21/768
2
US10468541B2
Semiconductor device with through-substrate via and corresponding method of manufacture
Publication/Patent Number: US10468541B2 Publication Date: 2019-11-05 Application Number: 15/107,901 Filing Date: 2014-12-12 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Loeffler, Bernhard   Holzhaider, Rainer   Assignee: ams AG   IPC: H01L31/0224 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.
3
US2016322519A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND CORRESPONDING METHOD OF MANUFACTURE
Publication/Patent Number: US2016322519A1 Publication Date: 2016-11-03 Application Number: 15/107,901 Filing Date: 2014-12-12 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Loeffler, Bernhard   Holzhaider, Rainer   Assignee: AMS AG   IPC: H01L31/0224 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.
4
WO2015097002A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND CORRESPONDING METHOD OF MANUFACTURE
Publication/Patent Number: WO2015097002A1 Publication Date: 2015-07-02 Application Number: 2014077587 Filing Date: 2014-12-12 Inventor: Schrank, Franz   Kraft, Jochen   Enichlmair, Hubert   Carniello, Sara   LÖffler, Bernhard   Holzhaider, Rainer   Assignee: AMS AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1)
5
EP2889901A1
Semiconductor device with through-substrate via and method of producing a semiconductor device with through-substrate via
Publication/Patent Number: EP2889901A1 Publication Date: 2015-07-01 Application Number: 13199683.7 Filing Date: 2013-12-27 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Löffler, Bernhard   Holzhaider, Rainer   Assignee: ams AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.