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1
US2021043590A1
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2021043590A1 Publication Date: 2021-02-11 Application Number: 17/080,826 Filing Date: 2020-10-26 Inventor: Hsu sen kuei   Pan, Hsin-yu   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/66 Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.
2
US2021043564A1
SEMICONDUCTOR DEVICE, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2021043564A1 Publication Date: 2021-02-11 Application Number: 17/079,525 Filing Date: 2020-10-26 Inventor: Hsu sen kuei   Pan, Hsin-yu   Chiang, Yi-che   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/522 Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
3
US10937734B2
Conductive traces in semiconductor devices and methods of forming same
Publication/Patent Number: US10937734B2 Publication Date: 2021-03-02 Application Number: 15/595,531 Filing Date: 2017-05-15 Inventor: Shih, Chao-wen   Yu, Chen-hua   Pu, Han-ping   Pan, Hsin-yu   Tsai, Hao-yi   Hsu sen kuei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/56 Abstract: A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.
4
US2020135670A1
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020135670A1 Publication Date: 2020-04-30 Application Number: 16/197,334 Filing Date: 2018-11-20 Inventor: Hsu sen kuei   Pan, Hsin-yu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/66 Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.
5
US10840197B2
Package structure and manufacturing method thereof
Publication/Patent Number: US10840197B2 Publication Date: 2020-11-17 Application Number: 16/197,334 Filing Date: 2018-11-20 Inventor: Hsu sen kuei   Pan, Hsin-yu   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/48 Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.
6
US10818588B2
Semiconductor device, package structure and method of fabricating the same
Publication/Patent Number: US10818588B2 Publication Date: 2020-10-27 Application Number: 16/262,924 Filing Date: 2019-01-31 Inventor: Hsu sen kuei   Pan, Hsin-yu   Chiang, Yi-che   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/10 Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
7
US2020243497A1
PACKAGE STRUCTURE
Publication/Patent Number: US2020243497A1 Publication Date: 2020-07-30 Application Number: 16/260,115 Filing Date: 2019-01-29 Inventor: Hsu sen kuei   Pan, Hsin-yu   Tsai, Ming-hsien   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L25/18 Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
8
US2020411499A1
PACKAGE STRUCTURE
Publication/Patent Number: US2020411499A1 Publication Date: 2020-12-31 Application Number: 17/022,064 Filing Date: 2020-09-15 Inventor: Hsu sen kuei   Pan, Hsin-yu   Tsai, Ming-hsien   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L25/18 Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
9
US2020251414A1
SEMICONDUCTOR DEVICE, PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2020251414A1 Publication Date: 2020-08-06 Application Number: 16/262,924 Filing Date: 2019-01-31 Inventor: Hsu sen kuei   Pan, Hsin-yu   Chiang, Yi-che   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/522 Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, a heat dissipation element and conductive balls. The insulating encapsulant is encapsulating the semiconductor die, and has a first surface and a second surface opposite to the first surface. The first redistribution layer is located on the first surface of the insulating encapsulant and includes at least one feed line and one ground plate. The second redistribution layer is located on the second surface of the insulating encapsulant and electrically connected to the semiconductor die and the first redistribution layer. The heat dissipation element is disposed on the first redistribution layer and includes a conductive base and antenna patterns, wherein the antenna patterns is electrically connected to the feed line and is electrically coupled to the ground plate of the first redistribution layer.
10
US10818651B2
Package structure
Publication/Patent Number: US10818651B2 Publication Date: 2020-10-27 Application Number: 16/260,115 Filing Date: 2019-01-29 Inventor: Hsu sen kuei   Pan, Hsin-yu   Tsai, Ming-hsien   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L25/18 Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
11
US2020373219A1
SEMICONDUCTOR PACKAGES HAVING THERMAL THROUGH VIAS (TTV)
Publication/Patent Number: US2020373219A1 Publication Date: 2020-11-26 Application Number: 16/993,285 Filing Date: 2020-08-14 Inventor: Hsu sen kuei   Yang, Ching-feng   Pan, Hsin-yu   Wu, Kai-chiang   Chiang, Yi-che   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/367 Abstract: A semiconductor package includes a die, a dummy die, a plurality of conductive terminals, an insulating layer and a plurality of thermal through vias. The dummy die is disposed aside the die. The conductive terminals are disposed at a first side of the dummy die and the die and electrically connected to the dummy die and the die. The insulating layer is disposed at a second side opposite to the first side of the dummy die and the die. The thermal through vias penetrating through the insulating layer.
12
US10867882B2
Semiconductor package, semiconductor device and method for packaging semiconductor device
Publication/Patent Number: US10867882B2 Publication Date: 2020-12-15 Application Number: 16/693,386 Filing Date: 2019-11-25 Inventor: Wan, Albert   Shih, Chao-wen   Pu, Han-ping   Pan, Hsin-yu   Hsu sen kuei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/34 Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.
13
US2020091031A1
SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE AND METHOD FOR PACKAGING SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020091031A1 Publication Date: 2020-03-19 Application Number: 16/693,386 Filing Date: 2019-11-25 Inventor: Wan, Albert   Shih, Chao-wen   Pu, Han-ping   Pan, Hsin-yu   Hsu sen kuei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/367 Abstract: A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.
14
US10748831B2
Semiconductor packages having thermal through vias (TTV)
Publication/Patent Number: US10748831B2 Publication Date: 2020-08-18 Application Number: 15/992,196 Filing Date: 2018-05-30 Inventor: Hsu sen kuei   Yang, Ching-feng   Pan, Hsin-yu   Wu, Kai-chiang   Chiang, Yi-che   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/36 Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor package includes a first die, a dummy die, a first redistribution layer structure, an insulating layer and an insulating layer. The dummy die is disposed aside the first die. The first redistribution layer structure is electrically connected to the first die and having connectors thereover. The insulating layer is disposed over the first die and the dummy die and opposite to the first redistribution layer structure. The insulating layer penetrates through the insulating layer.
15
US2020273773A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020273773A1 Publication Date: 2020-08-27 Application Number: 16/283,852 Filing Date: 2019-02-25 Inventor: Wan, Albert   Yu, Chen-hua   Liu, Chung-shi   Shih, Chao-wen   Pu, Han-ping   Pan, Hsin-yu   Hsu sen kuei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/373 Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.
16
US2020350782A1
Wireless Charging Devices Having Wireless Charging Coils and Methods of Manufacture Thereof
Publication/Patent Number: US2020350782A1 Publication Date: 2020-11-05 Application Number: 16/933,415 Filing Date: 2020-07-20 Inventor: Yu, Chen-hua   Chuang, Chita   Chen, Chen-shien   Tseng, Ming Hung   Hsu sen kuei   Chen, Yu-feng   Lin, Yen-liang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H02J50/10 Abstract: Wireless charging devices, methods of manufacture thereof, and methods of charging electronic devices are disclosed. In some embodiments, a wireless charging device includes a controller, a molding material disposed around the controller, and an interconnect structure disposed over the molding material and coupled to the controller. The wireless charging device includes a wireless charging coil coupled to the controller. The wireless charging coil comprises a first portion disposed in the interconnect structure and a second portion disposed in the molding material. The wireless charging coil is adapted to provide an inductance to charge an electronic device.
17
US10718790B2
Devices for high-density probing techniques and method of implementing the same
Publication/Patent Number: US10718790B2 Publication Date: 2020-07-21 Application Number: 16/378,288 Filing Date: 2019-04-08 Inventor: Wang, Mill-jer   Peng, Ching-nen   Lin, Hung-chih   Lin, Wei-hsun   Hsu sen kuei   Liu, De-jian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R1/073 Abstract: A testing apparatus with reduced warping of the probe card and a method of reducing warping of a probe card of a testing apparatus are disclosed. The testing apparatus can include a testing head and a platform opposite the testing head, where the testing head and platform move relative to one another to bring a sample into contact with probing tips of the testing apparatus. The testing head can include a probe card printed circuit board, a stiffener, a discontinuous backer and a plurality of probing tips. The stiffener can be coupled to and reinforcing the probe card. The discontinuous backer can extend from the probe card to the stiffener, and can include at least one unfilled void extending from the stiffener to the probe card. The plurality of probing tips can extend from a distal end of the testing head.
18
US10872842B2
Semiconductor device and manufacturing method thereof
Publication/Patent Number: US10872842B2 Publication Date: 2020-12-22 Application Number: 16/283,852 Filing Date: 2019-02-25 Inventor: Wan, Albert   Yu, Chen-hua   Liu, Chung-shi   Shih, Chao-wen   Pu, Han-ping   Pan, Hsin-yu   Hsu sen kuei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/66 Abstract: A semiconductor device including a chip package and an antenna package disposed on the chip package is provided. The chip package includes a semiconductor chip, an encapsulation enclosing the semiconductor chip, and a redistribution structure disposed on the semiconductor chip and the encapsulation and electrically coupled to the semiconductor chip. The antenna package includes an antenna pattern electrically coupled to the chip package, and an intermediate structure disposed between the antenna pattern and the chip package, wherein the intermediate structure comprises a ceramic element in contact with the redistribution structure and thermally dissipating a heat generated from the semiconductor chip.