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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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Inventor Inventor Assignee Assignee IPC IPC
1 US10277849B2
System and method for high-speed down-sampled CMOS image sensor readout
Publication/Patent Number: US10277849B2 Publication Date: 2019-04-30 Application Number: 15/941,431 Filing Date: 2018-03-30 Inventor: Chao, Calvin Yi-ping   Chang, Chin-hao   Chou, Kuo-yu   Yeh, Shang-fu   Lee, Chih-lin   Huang chiao yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/345 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
2 TW201801521A
System and method for high-speed down sampled CMOS image sensor readout
Publication/Patent Number: TW201801521A Publication Date: 2018-01-01 Application Number: 105135352 Filing Date: 2016-11-01 Inventor: Chou, Kuo-yu   Chang, Chin-hao   Yeh, Shang-fu   Huang chiao yi   Chao, Calvin Yi-ping   Lee, Chih-lin   Assignee: Taiwan Semiconductor Manufacturing Company Ltd.   IPC: H04N5/3745 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
3 US9955096B2
System and method for high-speed down-sampled CMOS image sensor readout
Publication/Patent Number: US9955096B2 Publication Date: 2018-04-24 Application Number: 15/076,983 Filing Date: 2016-03-22 Inventor: Huang chiao yi   Chou, Kuo-yu   Lee, Chih-lin   Chang, Chin-hao   Yeh, Shang-fu   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/378 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
4 US2018227531A1
SYSTEM AND METHOD FOR HIGH-SPEED DOWN-SAMPLED CMOS IMAGE SENSOR READOUT
Publication/Patent Number: US2018227531A1 Publication Date: 2018-08-09 Application Number: 15/941,431 Filing Date: 2018-03-30 Inventor: Huang chiao yi   Lee, Chih-lin   Yeh, Shang-fu   Chou, Kuo-yu   Chang, Chin-hao   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/378 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
5 US2017280086A1
SYSTEM AND METHOD FOR HIGH-SPEED DOWN-SAMPLED CMOS IMAGE SENSOR READOUT
Publication/Patent Number: US2017280086A1 Publication Date: 2017-09-28 Application Number: 15/076,983 Filing Date: 2016-03-22 Inventor: Chao, Calvin Yi-ping   Yeh, Shang-fu   Chang, Chin-hao   Lee, Chih-lin   Chou, Kuo-yu   Huang chiao yi   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H04N5/3745 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
6 US2015335274A1
PHYSIOLOGICAL SIGNALS DETECTION DEVICE
Publication/Patent Number: US2015335274A1 Publication Date: 2015-11-26 Application Number: 14/708,527 Filing Date: 2015-05-11 Inventor: Chang, Tom   Wu, Kao-pin   Fang, Chih-jen   Hung, Shang-ming   Huang chiao yi   Lo, Chan-peng   Kuo-tsai, Tseng   Assignee: EMINENT ELECTRONIC TECHNOLOGY CORP. LTD.   IPC: A61B5/1455 Abstract: A physiological signals detection device has a light source connecting to a control unit, a light detector and a processing unit. The light detector has a pixel sensor array including multiple light sensing elements. The light source emits light through a lens to the human body to generate reflected light. The light detector receives the reflected light to generate a sensing signal. Since the light sensing elements respectively receive different reflected light from different directions, the light sensing elements receiving reflected light from the noise are easily selected and eliminated from calculating the physiology value. Therefore, the calculated physiology value is more accurate.
7 TW201544070A
Physiological signals detection device
Publication/Patent Number: TW201544070A Publication Date: 2015-12-01 Application Number: 104111745 Filing Date: 2015-04-13 Inventor: Fang, Chih-jen   Lo, Chan-peng   Hung, Shang-ming   Huang chiao yi   Wu, Kao-pin   Kuotsai, Tseng   Chang, Tom Hong-de   Assignee: EMINENT ELECTRONIC TECHNOLOGY CORP. LTD.   IPC: A61B5/00 Abstract: The present invention relates to a physiological signals detection device. The physiological signals detection device has a light source connecting to a control unit
8 TWI422224B
Black level compensation circuit
Publication/Patent Number: TWI422224B Publication Date: 2014-01-01 Application Number: 100116805 Filing Date: 2011-05-13 Inventor: Liu, Chih Min   Huang chiao yi   Assignee: HIMAX IMAGING, INC.   IPC: H04N5/361 Abstract: A black level compensation circuit includes a first processing unit
9 TW201246928A
Black level compensation circuit
Publication/Patent Number: TW201246928A Publication Date: 2012-11-16 Application Number: 100116805 Filing Date: 2011-05-13 Inventor: Liu, Chih Min   Huang chiao yi   Assignee: HIMAX IMAGING, INC.   IPC: H04N5/361 Abstract: A black level compensation circuit includes a first processing unit