| No. | Publication Number | Title | Publication/Patent Number Publication/Patent Number |
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1 | US202006058A1 |
Conductive Feature Formation and Structure
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Publication/Patent Number: US202006058A1 | Publication Date: 2020-01-02 | Application Number: 20/191,656 | Filing Date: 2019-09-12 | Inventor： Wang, Chun-chieh Lin, Yu-ting Chang, Cheng-wei Huang huang yi Hung, Min-hsiu | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L23/532 | Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process. | |||
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2 | US2020043738A1 |
Wrap-Around Contact Plug and Method Manufacturing Same
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Publication/Patent Number: US2020043738A1 | Publication Date: 2020-02-06 | Application Number: 16/599,773 | Filing Date: 2019-10-11 | Inventor： Wang, Sung-li Sheu, Jyh-cherng Huang huang yi Chang, Chih-wei Chui, Chi On | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/285 | Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. | |||
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3 | US10636664B2 |
Wrap-around contact plug and method manufacturing same
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Publication/Patent Number: US10636664B2 | Publication Date: 2020-04-28 | Application Number: 16/599,773 | Filing Date: 2019-10-11 | Inventor： Wang, Sung-li Sheu, Jyh-cherng Huang huang yi Chang, Chih-wei Chui, Chi On | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/285 | Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. | |||
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4 | US2020258746A1 |
Wrap-Around Contact Plug and Method Manufacturing Same
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Publication/Patent Number: US2020258746A1 | Publication Date: 2020-08-13 | Application Number: 16/859,125 | Filing Date: 2020-04-27 | Inventor： Wang, Sung-li Sheu, Jyh-cherng Huang huang yi Chang, Chih-wei Chui, Chi On | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/285 | Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. | |||
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5 | US2020006058A1 |
Conductive Feature Formation and Structure
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Publication/Patent Number: US2020006058A1 | Publication Date: 2020-01-02 | Application Number: 16/568,720 | Filing Date: 2019-09-12 | Inventor： Chang, Cheng-wei Hung, Min-hsiu Huang huang yi Wang, Chun-chieh Lin, Yu-ting | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/02 | Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process. | |||
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6 | US202043738A1 |
Wrap-Around Contact Plug and Method Manufacturing Same
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Publication/Patent Number: US202043738A1 | Publication Date: 2020-02-06 | Application Number: 20/191,659 | Filing Date: 2019-10-11 | Inventor： Sheu, Jyh-cherng Chang, Chih-wei Wang, Sung-li Huang huang yi Chui, Chi On | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L29/78 | Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. | |||
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7 | US10879075B2 |
Wrap-around contact plug and method manufacturing same
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Publication/Patent Number: US10879075B2 | Publication Date: 2020-12-29 | Application Number: 16/859,125 | Filing Date: 2020-04-27 | Inventor： Wang, Sung-li Sheu, Jyh-cherng Huang huang yi Chang, Chih-wei Chui, Chi On | Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. | IPC: H01L21/285 | Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. | |||
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8 | US10714334B2 |
Conductive feature formation and structure
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Publication/Patent Number: US10714334B2 | Publication Date: 2020-07-14 | Application Number: 15/860,354 | Filing Date: 2018-01-02 | Inventor： Chang, Cheng-wei Huang huang yi Wang, Chun-chieh Lin, Yu-ting Hung, Min-hsiu | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/762 | Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process. | |||
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9 | US10685842B2 |
Selective formation of titanium silicide and titanium nitride by hydrogen gas control
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Publication/Patent Number: US10685842B2 | Publication Date: 2020-06-16 | Application Number: 15/983,216 | Filing Date: 2018-05-18 | Inventor： Chang, Cheng-wei Lin, Kao-feng Hung, Min-hsiu Chao, Yi-hsiang Huang huang yi Lin, Yu-ting | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/285 | Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow. | |||
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10 | US2020294807A1 |
SELECTIVE FORMATION OF TITANIUM SILICIDE AND TITANIUM NITRIDE BY HYDROGEN GAS CONTROL
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Publication/Patent Number: US2020294807A1 | Publication Date: 2020-09-17 | Application Number: 16/887,218 | Filing Date: 2020-05-29 | Inventor： Chang, Cheng-wei Lin, Kao-feng Hung, Min-hsiu Chao, Yi-hsiang Huang huang yi Lin, Yu-ting | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/285 | Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow. | |||
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11 | US2020335597A1 |
SEMICONDUCTOR DEVICE WITH LOW RESISTIVITY CONTACT STRUCTURE
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Publication/Patent Number: US2020335597A1 | Publication Date: 2020-10-22 | Application Number: 16/914,638 | Filing Date: 2020-06-29 | Inventor： Hung, Min-hsiu Chao, Yi-hsiang Yeh, Kuan-yu Lin, Kan-ju Nieh, Chun-wen Huang huang yi Chang, Chih-wei Su, Ching-hwanq | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L29/45 | Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements. | |||
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12 | US10700177B2 |
Semiconductor device with low resistivity contact structure and method for forming the same
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Publication/Patent Number: US10700177B2 | Publication Date: 2020-06-30 | Application Number: 15/964,352 | Filing Date: 2018-04-27 | Inventor： Hung, Min-hsiu Chao, Yi-hsiang Yeh, Kuan-yu Lin, Kan-ju Nieh, Chun-wen Huang huang yi Chang, Chih-wei Su, Ching-hwanq | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L29/45 | Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening. | |||
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13 | US2020118935A1 |
CONTACT STRUCTURE AND FORMATION THEREOF
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Publication/Patent Number: US2020118935A1 | Publication Date: 2020-04-16 | Application Number: 16/716,441 | Filing Date: 2019-12-16 | Inventor： Lee, Hong-mao Chang, Huicheng Lai, Chia-han Ni, Chi-hsuan Lin, Cheng-tung Huang huang yi Chen, Chi-yuan Wang, Li-ting Tsai, Teng-chun Lin, Wei-jung | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED | IPC: H01L23/532 | Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity. | |||
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14 | US10658234B2 |
Formation method of interconnection structure of semiconductor device
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Publication/Patent Number: US10658234B2 | Publication Date: 2020-05-19 | Application Number: 15/223,902 | Filing Date: 2016-07-29 | Inventor： Hung, Min-hsiu Wang, Sung-li Wu, Pei-wen Li, Yida Chang, Chih-wei Huang huang yi Lin, Cheng-tung Sheu, Jyh-cherng Yeo, Yee-chia Chui, Chi-on | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L21/44 | Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region. | |||
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15 | TWI674650B |
Wrap-around contact plug and method manufacturing same
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Publication/Patent Number: TWI674650B | Publication Date: 2019-10-11 | Application Number: 106135914 | Filing Date: 2017-10-19 | Inventor： Chang, Chih Wei Wang, Sung Li Huang, Huang Yi Chui, Chi On Sheu, Jyh Cheng | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/768 | Abstract: A method for manufacturing a semiconductor device includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, performing a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. | |||
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16 | KR20190024536A |
WRAP-AROUND CONTACT PLUG AND METHOD MANUFACTURING SAME
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Publication/Patent Number: KR20190024536A | Publication Date: 2019-03-08 | Application Number: 20170166775 | Filing Date: 2017-12-06 | Inventor： Chang, Chih Wei Chui, Chi On Wang, Sung Li Huang, Huang Yi Sheu, Jyh Cherng | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L29/78 | Abstract: A manufacturing method of a wrap-around contact plug comprises the steps of: forming a source/drain region; and performing selective deposition for forming a metal silicide layer on the source/drain region and forming a metal layer on a dielectric region adjacent to the source/drain region in a vacuum chamber or a vacuum cluster system. The manufacturing method also comprises the steps of: selectively etching the metal layer in the vacuum chamber; and selectively forming a metal nitride layer on the metal silicide layer. The step of selectively forming the metal nitride layer is performed in the vacuum chamber or the vacuum cluster system without breaking the vacuum. | |||
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17 | TW201913885A |
Wrap-around contact plug and method manufacturing same
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Publication/Patent Number: TW201913885A | Publication Date: 2019-04-01 | Application Number: 106135914 | Filing Date: 2017-10-19 | Inventor： Chang, Chih Wei Wang, Sung Li Huang, Huang Yi Chui, Chi On Sheu, Jyh Cheng | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/768 | Abstract: A method for manufacturing a semiconductor device includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, performing a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break. | |||
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18 | KR102010188B1 |
METHOD FOR INTEGRATED CIRCUIT PATTERNING
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Publication/Patent Number: KR102010188B1 | Publication Date: 2019-08-12 | Application Number: 20180095457 | Filing Date: 2018-08-16 | Inventor： Huang, Huang Yi Tung, Szu Ping Yang, Neng Jye Hsieh, Ching Hua | Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. | IPC: H01L21/033 | Abstract: The present invention relates to a method for forming a target pattern. The method includes a step of forming a plurality of lines on a substrate using a first mask and a step of forming a spacer layer on the substrate, the lines, and side walls of the lines. In addition, the method includes a step of removing at least a part of the spacer layer to expose the lines and the substrate. Moreover, the method includes a step of shrinking the spacer layer disposed on the side walls of the lines and a step of providing the patterned spacer layer on the substrate by removing the lines. Therefore, an improved method for patterning an integrated circuit may be provided. | |||
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19 | TW201925525A |
Conductive feature formation and structure
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Publication/Patent Number: TW201925525A | Publication Date: 2019-07-01 | Application Number: 107116123 | Filing Date: 2018-05-11 | Inventor： Wang, Chun Chieh Lin, Yu Ting Huang, Huang Yi Chang, Cheng Wei Hung, Min Hsiu | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/205 | Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process. | |||
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20 | TWI671432B |
Conductive feature formation and structure
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Publication/Patent Number: TWI671432B | Publication Date: 2019-09-11 | Application Number: 107116123 | Filing Date: 2018-05-11 | Inventor： Wang, Chun Chieh Lin, Yu Ting Huang, Huang Yi Chang, Cheng Wei Hung, Min Hsiu | Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. | IPC: H01L21/205 | Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process. |
3.Current Quota