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1
US10566374B2
Via support structure under pad areas for BSI bondability improvement
Publication/Patent Number: US10566374B2 Publication Date: 2020-02-18 Application Number: 16/167,844 Filing Date: 2018-10-23 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.
2
US2020135794A1
VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT
Publication/Patent Number: US2020135794A1 Publication Date: 2020-04-30 Application Number: 16/732,646 Filing Date: 2020-01-02 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire disposed within a dielectric structure on a substrate. A bond pad has a lower surface contacting the first interconnect wire. A via layer is vertically between the first interconnect wire and a second interconnect wire within the dielectric structure. The via layer includes a plurality of support vias having a first size and a plurality of additional vias having a second size that is smaller than the first size. The plurality of support vias extend from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad.
3
US2020013736A1
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2020013736A1 Publication Date: 2020-01-09 Application Number: 16/574,185 Filing Date: 2019-09-18 Inventor: Yang, Ming-hsien   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Huang sin yao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/00 Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure.
4
US202013736A1
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US202013736A1 Publication Date: 2020-01-09 Application Number: 20/191,657 Filing Date: 2019-09-18 Inventor: Yaung, Dun-nian   Wang, Ching-chun   Hung, Feng-chi   Huang sin yao   Yang, Ming-hsien   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure.
5
US2020152675A1
BOND PAD STRUCTURE FOR BONDING IMPROVEMENT
Publication/Patent Number: US2020152675A1 Publication Date: 2020-05-14 Application Number: 16/705,376 Filing Date: 2019-12-06 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Wang, Ming-tsong   Chou, Shih Pei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.
6
US10283549B2
Via support structure under pad areas for BSI bondability improvement
Publication/Patent Number: US10283549B2 Publication Date: 2019-05-07 Application Number: 16/046,183 Filing Date: 2018-07-26 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments of the present disclosure relate to a method of forming an integrated chip. The method includes forming a first interconnect wire within a first inter-level dielectric (ILD) layer over a substrate. One or more vias are formed on the first interconnect wire and within a second ILD layer separated from the substrate by the first ILD layer. One or more additional vias are formed within the second ILD layer. Respective ones of the one or more vias have a larger size than respective ones of the one or more additional vias. A thickness of the substrate is reduced, and the substrate is etched to form a bond pad opening extending through the substrate to the first interconnect wire. A bond pad is formed within the bond pad opening and directly over the one or more vias.
7
US201957998A1
VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT
Publication/Patent Number: US201957998A1 Publication Date: 2019-02-21 Application Number: 20/181,616 Filing Date: 2018-10-23 Inventor: Yaung, Dun-nian   Wang, Ching-chun   Hung, Feng-chi   Huang sin yao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.
8
US2019057998A1
VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT
Publication/Patent Number: US2019057998A1 Publication Date: 2019-02-21 Application Number: 16/167,844 Filing Date: 2018-10-23 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.
9
US10475758B2
Semiconductor device structure and method for forming the same
Publication/Patent Number: US10475758B2 Publication Date: 2019-11-12 Application Number: 15/880,684 Filing Date: 2018-01-26 Inventor: Yang, Ming-hsien   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Huang sin yao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface opposing the first surface, and sidewalls defining a recess that passes through the semiconductor substrate. A first interconnect layer is within a first dielectric structure disposed along the second surface, and a bonding pad is in the recess and extends to the first interconnect layer. A dielectric filling layer is also within the recess. The dielectric filling layer has an opening over a portion of the bonding pad and a curved upper surface over the bonding pad. A nickel layer is over the bonding pad and in the opening.
10
US10269770B2
Hybrid bond pad structure
Publication/Patent Number: US10269770B2 Publication Date: 2019-04-23 Application Number: 15/626,834 Filing Date: 2017-06-19 Inventor: Huang sin yao   Chuang, Chun-chieh   Wang, Ching-chun   Chen, Sheng-chau   Yaung, Dun-nian   Hung, Feng-chi   Lin, Yung-lung   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L25/065 Abstract: In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between integrated chip die at a location laterally offset from a bond pad. The integrated chip structure has a first die and a second die. The first die has a first plurality of interconnect layers arranged within a first dielectric structure disposed on a first substrate. The second die has a second plurality of interconnect layers arranged within a second dielectric structure disposed between the first dielectric structure and a second substrate. A bond pad is disposed within a recess extending through the second substrate. A redistribution structure electrically couples the first die to the second die at a position that is laterally offset from the bond pad.
11
US10515995B2
Bond pad structure for bonding improvement
Publication/Patent Number: US10515995B2 Publication Date: 2019-12-24 Application Number: 16/043,919 Filing Date: 2018-07-24 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Wang, Ming-tsong   Chou, Shih Pei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.
12
US2019221548A1
HYBRID BOND PAD STRUCTURE
Publication/Patent Number: US2019221548A1 Publication Date: 2019-07-18 Application Number: 16/367,720 Filing Date: 2019-03-28 Inventor: Huang sin yao   Chuang, Chun-chieh   Wang, Ching-chun   Chen, Sheng-chau   Yaung, Dun-nian   Hung, Feng-chi   Lin, Yung-lung   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L25/065 Abstract: In some embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method includes forming a first plurality of interconnect layers within a first dielectric structure on a front-side of a first substrate and forming a second plurality of interconnect layers within a second dielectric structure on a front-side of a second substrate. A first redistribution layer coupled to the first plurality of interconnect layers is bonded to a second redistribution layer coupled to the second plurality of interconnect layers along an interface. A recess is formed within a back-side of the second substrate and over the second plurality of interconnect layers. A bond pad is formed within the recess. The bond pad is laterally separated from the first redistribution layer by a non-zero distance.
13
US2018350865A1
VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT
Publication/Patent Number: US2018350865A1 Publication Date: 2018-12-06 Application Number: 16/046,183 Filing Date: 2018-07-26 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments of the present disclosure relate to a method of forming an integrated chip. The method includes forming a first interconnect wire within a first inter-level dielectric (ILD) layer over a substrate. One or more vias are formed on the first interconnect wire and within a second ILD layer separated from the substrate by the first ILD layer. One or more additional vias are formed within the second ILD layer. Respective ones of the one or more vias have a larger size than respective ones of the one or more additional vias. A thickness of the substrate is reduced, and the substrate is etched to form a bond pad opening extending through the substrate to the first interconnect wire. A bond pad is formed within the bond pad opening and directly over the one or more vias.
14
US10038025B2
Via support structure under pad areas for BSI bondability improvement
Publication/Patent Number: US10038025B2 Publication Date: 2018-07-31 Application Number: 15/380,186 Filing Date: 2016-12-15 Inventor: Hung, Feng-chi   Yaung, Dun-nian   Wang, Ching-chun   Huang sin yao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments of the present disclosure relate to an integrated chip having a via support structure underlying a bond pad. The integrated chip has an image sensing element arranged within a substrate. A bond pad region extends through the substrate, at a location laterally offset from the image sensing element, to a first metal interconnect wire arranged within a dielectric structure along a front-side of the substrate. A bond pad is arranged within the bond pad region and contacts the first metal interconnect wire. A via support structure is arranged within the dielectric structure and has one or more vias that are separated from the bond pad by the first metal interconnect wire. One or more additional vias are arranged within the dielectric structure at a location laterally offset from the bond pad region. The one or more vias have larger sizes than the one or more additional vias.
15
US2018151522A1
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2018151522A1 Publication Date: 2018-05-31 Application Number: 15/880,684 Filing Date: 2018-01-26 Inventor: Huang sin yao   Hung, Feng-chi   Yaung, Dun-nian   Wang, Ching-chun   Yang, Ming-hsien   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface opposing the first surface, and sidewalls defining a recess that passes through the semiconductor substrate. A first interconnect layer is within a first dielectric structure disposed along the second surface, and a bonding pad is in the recess and extends to the first interconnect layer. A dielectric filling layer is also within the recess. The dielectric filling layer has an opening over a portion of the bonding pad and a curved upper surface over the bonding pad. A nickel layer is over the bonding pad and in the opening.
16
US9881884B2
Semiconductor device structure and method for forming the same
Publication/Patent Number: US9881884B2 Publication Date: 2018-01-30 Application Number: 14/933,619 Filing Date: 2015-11-05 Inventor: Yaung, Dun-nian   Wang, Ching-chun   Hung, Feng-chi   Huang sin yao   Yang, Ming-hsien   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   TAIWAN SEMICONDUCTOR_2   IPC: H01L27/146 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite to the first surface. The recess passes through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer over the second surface. The semiconductor device structure includes a first bonding pad in the recess and extending to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bonding pad. The semiconductor device structure includes a gold layer over the nickel layer.
17
US2018350857A1
BOND PAD STRUCTURE FOR BONDING IMPROVEMENT
Publication/Patent Number: US2018350857A1 Publication Date: 2018-12-06 Application Number: 16/043,919 Filing Date: 2018-07-24 Inventor: Huang sin yao   Wang, Ching-chun   Yaung, Dun-nian   Hung, Feng-chi   Wang, Ming-tsong   Chou, Shih Pei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.
18
US10038026B2
Bond pad structure for bonding improvement
Publication/Patent Number: US10038026B2 Publication Date: 2018-07-31 Application Number: 15/088,232 Filing Date: 2016-04-01 Inventor: Chou, Shih Pei   Wang, Ming-tsong   Hung, Feng-chi   Yaung, Dun-nian   Wang, Ching-chun   Huang sin yao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate, and includes a plurality of metal layers and insulating layers that are over stacked over one another in alternating fashion. One of the plurality of metal layers is closest to the light source and another of the plurality of metal layers is furthest from the light source. A bond pad recess extends into the interconnect structure from an opening in a surface of the 3DIC which is nearest the light source and terminates at a bond pad. The bond pad is spaced apart from the surface of the 3DIC and is in direct contact with the one of the plurality of metal layers that is furthest from the light source.
19
KR20170020198A
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: KR20170020198A Publication Date: 2017-02-22 Application Number: 20160010589 Filing Date: 2016-01-28 Inventor: Yaung, Dun Nian   Hung, Feng Chi   Wang, Ching Chun   Yang, Ming Hsien   Huang sin yao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate which includes a first surface
20
TW201712846A
IC
Publication/Patent Number: TW201712846A Publication Date: 2017-04-01 Application Number: 105119695 Filing Date: 2016-06-23 Inventor: Yaung, Dun Nian   Wang, Ching Chun   Huang sin yao   Hung, Feng Chi   Wang, Ming Tsong   Chou, Shih Pei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L25/065 Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3DIC includes a first substrate including a photodetector which is configured to receive light in a first direction from a light source. An interconnect structure is disposed over the first substrate