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1
US10886320B2
Mechanisms for forming image-sensor device with epitaxial isolation feature
Publication/Patent Number: US10886320B2 Publication Date: 2021-01-05 Application Number: 16/387,989 Filing Date: 2019-04-18 Inventor: Hsu, Wen-i   Hung feng chi   Chuang, Chun-chieh   Yaung, Dun-nian   Liu, Jen-cheng   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
2
US2021005649A1
SEMICONDUCTOR IMAGING DEVICE HAVING IMPROVED DARK CURRENT PERFORMANCE
Publication/Patent Number: US2021005649A1 Publication Date: 2021-01-07 Application Number: 17/022,456 Filing Date: 2020-09-16 Inventor: Takahashi, Seiji   Wang, Chen-jong   Yaung, Dun-nian   Hung feng chi   Shiu, Feng-jia   Liu, Jen-cheng   Sze, Jhy-jyi   Chang, Chun-wei   Hsu, Wei-cheng   Wu, Wei Chuang   Huang, Yimin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.
3
US2020303429A1
MECHANISMS FOR FORMING IMAGE-SENSOR DEVICE WITH DEEP-TRENCH ISOLATION STRUCTURE
Publication/Patent Number: US2020303429A1 Publication Date: 2020-09-24 Application Number: 16/889,161 Filing Date: 2020-06-01 Inventor: Lin, Jeng-shyan   Yaung, Dun-nian   Liu, Jen-cheng   Hung feng chi   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L27/146 Abstract: An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region in the semiconductor substrate and a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region.
4
US2020135794A1
VIA SUPPORT STRUCTURE UNDER PAD AREAS FOR BSI BONDABILITY IMPROVEMENT
Publication/Patent Number: US2020135794A1 Publication Date: 2020-04-30 Application Number: 16/732,646 Filing Date: 2020-01-02 Inventor: Huang, Sin-yao   Wang, Ching-chun   Yaung, Dun-nian   Hung feng chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect wire disposed within a dielectric structure on a substrate. A bond pad has a lower surface contacting the first interconnect wire. A via layer is vertically between the first interconnect wire and a second interconnect wire within the dielectric structure. The via layer includes a plurality of support vias having a first size and a plurality of additional vias having a second size that is smaller than the first size. The plurality of support vias extend from directly under the lower surface of the bond pad to laterally past outermost edges of the lower surface of the bond pad.
5
US10566374B2
Via support structure under pad areas for BSI bondability improvement
Publication/Patent Number: US10566374B2 Publication Date: 2020-02-18 Application Number: 16/167,844 Filing Date: 2018-10-23 Inventor: Huang, Sin-yao   Wang, Ching-chun   Yaung, Dun-nian   Hung feng chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a substrate and a first interconnect wire arranged within a dielectric structure on the substrate. A bond pad contacts the first interconnect wire. A via support structure has one or more vias arranged within the dielectric structure at a location separated from the substrate by the first interconnect wire, The via support structure has a metal pattern density that is greater than or equal to approximately 19% and that is configured to mitigate damage caused by a force of a bonding process on the bond pad.
6
US10672819B2
Mechanisms for forming image-sensor device with deep-trench isolation structure
Publication/Patent Number: US10672819B2 Publication Date: 2020-06-02 Application Number: 16/193,159 Filing Date: 2018-11-16 Inventor: Lin, Jeng-shyan   Yaung, Dun-nian   Liu, Jen-cheng   Hung feng chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: An image-sensor device is provided. The image-sensor device includes a substrate having a front side and a back side. The image-sensor device also includes a radiation-sensing region operable to detect incident radiation that enters the substrate through the back side. The image-sensor device further includes a deep-trench isolation structure extending from the back side towards the front side. The deep-trench isolation structure includes a dielectric layer, and the dielectric layer contains hafnium or aluminum.
7
US202013736A1
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US202013736A1 Publication Date: 2020-01-09 Application Number: 20/191,657 Filing Date: 2019-09-18 Inventor: Yaung, Dun-nian   Wang, Ching-chun   Hung feng chi   Huang, Sin-yao   Yang, Ming-hsien   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure.
8
US2020013736A1
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2020013736A1 Publication Date: 2020-01-09 Application Number: 16/574,185 Filing Date: 2019-09-18 Inventor: Yang, Ming-hsien   Wang, Ching-chun   Yaung, Dun-nian   Hung feng chi   Huang, Sin-yao   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/00 Abstract: A semiconductor device structure is provided, in some embodiments. The semiconductor device structure includes a semiconductor substrate having a first surface, a second surface, and sidewalls defining a recess that passes through the semiconductor substrate. The semiconductor device structure further includes an interconnect structure having one or more interconnect layers within a first dielectric structure that is disposed along the second surface. A conductive bonding structure is disposed within the recess and includes nickel. The conductive bonding structure has opposing outermost sidewalls that contact sidewalls of the interconnect structure.
9
US10734428B2
Image sensor device
Publication/Patent Number: US10734428B2 Publication Date: 2020-08-04 Application Number: 16/212,784 Filing Date: 2018-12-07 Inventor: Chen, Szu-ying   Kao, Min-feng   Liu, Jen-cheng   Hung feng chi   Yaung, Dun-nian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device has a gate stack arranged over a first surface of a substrate. A doped isolation feature is arranged within the substrate along opposing sides of the gate stack. A photodetector is also arranged within the substrate. An isolation well region extends below the gate stack and contacts the doped isolation feature along a horizontal plane that is parallel to the first surface and that intersects sides of the photodetector.
10
US2020321373A1
IMAGE SENSOR DEVICE
Publication/Patent Number: US2020321373A1 Publication Date: 2020-10-08 Application Number: 16/909,024 Filing Date: 2020-06-23 Inventor: Chen, Szu-ying   Kao, Min-feng   Liu, Jen-cheng   Hung feng chi   Yaung, Dun-nian   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure arranged on a first surface of a substrate. A doped isolation region is arranged within the substrate along opposing sides of the gate structure. The substrate includes a first region between sides of the doped isolation region and a second region having a different doping characteristic than the first region. The second region contacts a bottom of the first region and a bottom of the doped isolation region.
11
US2020127027A1
Interconnect Structure for Stacked Device and Method
Publication/Patent Number: US2020127027A1 Publication Date: 2020-04-23 Application Number: 16/723,467 Filing Date: 2019-12-20 Inventor: Chuang, Chun-chieh   Yaung, Dun-nian   Liu, Jen-cheng   Hung feng chi   Hsu, Tzu-hsuan   Tsai, Shu-ting   Kao, Min-feng   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/146 Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
12
US2020258865A1
Stacked Integrated Circuits with Redistribution Lines
Publication/Patent Number: US2020258865A1 Publication Date: 2020-08-13 Application Number: 16/853,293 Filing Date: 2020-04-20 Inventor: Ho, Cheng-ying   Lin, Jeng-shyan   Hsu, Wen-i   Hung feng chi   Yaung, Dun-nian   Tsai, Ying-ling   Hsu, Wen-i   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L25/065 Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
13
US2020306552A1
Interconnect Structure and Method of Forming Same
Publication/Patent Number: US2020306552A1 Publication Date: 2020-10-01 Application Number: 16/901,884 Filing Date: 2020-06-15 Inventor: Tsai, Shu-ting   Lin, Jeng-shyan   Chuang, Chun-chieh   Yaung, Dun-nian   Liu, Jen-cheng   Hung feng chi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: A61N1/39 Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
14
US10682523B2
Interconnect structure and method of forming same
Publication/Patent Number: US10682523B2 Publication Date: 2020-06-16 Application Number: 16/154,154 Filing Date: 2018-10-08 Inventor: Tsai, Shu-ting   Lin, Jeng-shyan   Chuang, Chun-chieh   Yaung, Dun-nian   Liu, Jen-cheng   Hung feng chi   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/48 Abstract: A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component.
15
US10629568B2
Stacked integrated circuits with redistribution lines
Publication/Patent Number: US10629568B2 Publication Date: 2020-04-21 Application Number: 16/390,894 Filing Date: 2019-04-22 Inventor: Ho, Cheng-ying   Lin, Jeng-shyan   Hsu, Wen-i   Hung feng chi   Yaung, Dun-nian   Tsai, Ying-ling   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L25/065 Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
16
US10535706B2
Interconnect structure for stacked device and method
Publication/Patent Number: US10535706B2 Publication Date: 2020-01-14 Application Number: 16/220,441 Filing Date: 2018-12-14 Inventor: Chuang, Chun-chieh   Yaung, Dun-nian   Liu, Jen-cheng   Hung feng chi   Hsu, Tzu-hsuan   Tsai, Shu-ting   Kao, Min-feng   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: H01L21/00 Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
17
US2020243580A1
MANUFACTURING METHOD OF IMAGE SENSING DEVICE
Publication/Patent Number: US2020243580A1 Publication Date: 2020-07-30 Application Number: 16/842,909 Filing Date: 2020-04-08 Inventor: Wu, Wei-chuang   Wang, Ming-tsong   Hung feng chi   Wang, Ching-chun   Liu, Jen-cheng   Yaung, Dun-nian   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L27/146 Abstract: A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials.
18
US2020083049A1
Gate Electrodes with Notches and Methods for Forming the Same
Publication/Patent Number: US2020083049A1 Publication Date: 2020-03-12 Application Number: 16/685,480 Filing Date: 2019-11-15 Inventor: Kao, Min-feng   Chen, Szu-ying   Yaung, Dun-nian   Liu, Jen-cheng   Hsu, Tzu-hsuan   Hung feng chi   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/265 Abstract: A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.
19
US2020152675A1
BOND PAD STRUCTURE FOR BONDING IMPROVEMENT
Publication/Patent Number: US2020152675A1 Publication Date: 2020-05-14 Application Number: 16/705,376 Filing Date: 2019-12-06 Inventor: Huang, Sin-yao   Wang, Ching-chun   Yaung, Dun-nian   Hung feng chi   Wang, Ming-tsong   Chou, Shih Pei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L27/146 Abstract: Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.
20
US10763292B2
Interconnect apparatus and method for a stacked semiconductor device
Publication/Patent Number: US10763292B2 Publication Date: 2020-09-01 Application Number: 16/224,300 Filing Date: 2018-12-18 Inventor: Lin, Jeng-shyan   Tsai, Shu-ting   Yaung, Dun-nian   Liu, Jen-cheng   Hung feng chi   Chou, Shih-pei   Kao, Min-feng   Chen, Szu-ying   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L27/146 Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.