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1
US2021074580A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2021074580A1 Publication Date: 2021-03-11 Application Number: 17/101,858 Filing Date: 2020-11-23 Inventor: Chen, Pin-wen   Lai, Chia-han   Fu, Mei-hui   Hung min hsiu   Cheng, Ya-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
2
US2021013033A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2021013033A1 Publication Date: 2021-01-14 Application Number: 17/036,734 Filing Date: 2020-09-29 Inventor: Chang, Cheng-wei   Hung min hsiu   Huang, Hung-yi   Wang, Chun Chieh   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
3
US202006058A1
Conductive Feature Formation and Structure
Publication/Patent Number: US202006058A1 Publication Date: 2020-01-02 Application Number: 20/191,656 Filing Date: 2019-09-12 Inventor: Wang, Chun-chieh   Lin, Yu-ting   Chang, Cheng-wei   Huang, Huang-yi   Hung min hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
4
US2020006058A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2020006058A1 Publication Date: 2020-01-02 Application Number: 16/568,720 Filing Date: 2019-09-12 Inventor: Chang, Cheng-wei   Hung min hsiu   Huang, Huang-yi   Wang, Chun-chieh   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
5
US10714334B2
Conductive feature formation and structure
Publication/Patent Number: US10714334B2 Publication Date: 2020-07-14 Application Number: 15/860,354 Filing Date: 2018-01-02 Inventor: Chang, Cheng-wei   Huang, Huang-yi   Wang, Chun-chieh   Lin, Yu-ting   Hung min hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/762 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
6
US2020176260A1
FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING THE SAME
Publication/Patent Number: US2020176260A1 Publication Date: 2020-06-04 Application Number: 16/265,747 Filing Date: 2019-02-01 Inventor: Hung min hsiu   Chang, Chien   Chao, Yi-hsiang   Huang, Hung-yi   Chang, Chih-wei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/285 Abstract: A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.
7
US10804140B2
Interconnect formation and structure
Publication/Patent Number: US10804140B2 Publication Date: 2020-10-13 Application Number: 15/939,572 Filing Date: 2018-03-29 Inventor: Chen, Pin-wen   Lai, Chia-han   Fu, Mei-hui   Hung min hsiu   Cheng, Ya-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
8
US10847411B2
Conductive feature formation and structure
Publication/Patent Number: US10847411B2 Publication Date: 2020-11-24 Application Number: 16/556,383 Filing Date: 2019-08-30 Inventor: Chen, Pin-wen   Lai, Chia-han   Fu, Mei-hui   Hung min hsiu   Cheng, Ya-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
9
US10804097B2
Conductive feature formation and structure
Publication/Patent Number: US10804097B2 Publication Date: 2020-10-13 Application Number: 16/568,720 Filing Date: 2019-09-12 Inventor: Chang, Cheng-wei   Hung min hsiu   Huang, Hung-yi   Wang, Chun Chieh   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
10
US10685842B2
Selective formation of titanium silicide and titanium nitride by hydrogen gas control
Publication/Patent Number: US10685842B2 Publication Date: 2020-06-16 Application Number: 15/983,216 Filing Date: 2018-05-18 Inventor: Chang, Cheng-wei   Lin, Kao-feng   Hung min hsiu   Chao, Yi-hsiang   Huang, Huang-yi   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/285 Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
11
US10700177B2
Semiconductor device with low resistivity contact structure and method for forming the same
Publication/Patent Number: US10700177B2 Publication Date: 2020-06-30 Application Number: 15/964,352 Filing Date: 2018-04-27 Inventor: Hung min hsiu   Chao, Yi-hsiang   Yeh, Kuan-yu   Lin, Kan-ju   Nieh, Chun-wen   Huang, Huang-yi   Chang, Chih-wei   Su, Ching-hwanq   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L29/45 Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate including a conductive region made of silicon, germanium or a combination thereof. The method also includes forming an insulating layer over the semiconductor substrate and forming an opening in the insulating layer to expose the conductive region. The method also includes performing a deposition process to form a metal layer over a sidewall and a bottom of the opening, so that a metal silicide or germanide layer is formed on the exposed conductive region by the deposition process. The method also includes performing a first in-situ etching process to etch at least a portion of the metal layer and forming a fill metal material layer in the opening.
12
US2020335597A1
SEMICONDUCTOR DEVICE WITH LOW RESISTIVITY CONTACT STRUCTURE
Publication/Patent Number: US2020335597A1 Publication Date: 2020-10-22 Application Number: 16/914,638 Filing Date: 2020-06-29 Inventor: Hung min hsiu   Chao, Yi-hsiang   Yeh, Kuan-yu   Lin, Kan-ju   Nieh, Chun-wen   Huang, Huang-yi   Chang, Chih-wei   Su, Ching-hwanq   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/45 Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.
13
US2020294807A1
SELECTIVE FORMATION OF TITANIUM SILICIDE AND TITANIUM NITRIDE BY HYDROGEN GAS CONTROL
Publication/Patent Number: US2020294807A1 Publication Date: 2020-09-17 Application Number: 16/887,218 Filing Date: 2020-05-29 Inventor: Chang, Cheng-wei   Lin, Kao-feng   Hung min hsiu   Chao, Yi-hsiang   Huang, Huang-yi   Lin, Yu-ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/285 Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
14
US10658234B2
Formation method of interconnection structure of semiconductor device
Publication/Patent Number: US10658234B2 Publication Date: 2020-05-19 Application Number: 15/223,902 Filing Date: 2016-07-29 Inventor: Hung min hsiu   Wang, Sung-li   Wu, Pei-wen   Li, Yida   Chang, Chih-wei   Huang, Huang-yi   Lin, Cheng-tung   Sheu, Jyh-cherng   Yeo, Yee-chia   Chui, Chi-on   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/44 Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.
15
US2020020583A1
FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL-SEMICONDUCTOR COMPOUND REGION
Publication/Patent Number: US2020020583A1 Publication Date: 2020-01-16 Application Number: 16/034,843 Filing Date: 2018-07-13 Inventor: Chao, Yi-hsiang   Hung min hsiu   Nieh, Chun-wen   Li, Ya-huei   Liao, Yu-hsiang   Chu, Li-wei   Lin, Kan-ju   Yeh, Kuan-yu   Chuang, Chi-hung   Chang, Chih-wei   Su, Ching-hwanq   Huang, Hung-yi   Tsai, Ming-hsing   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
16
US202020583A1
FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH METAL-SEMICONDUCTOR COMPOUND REGION
Publication/Patent Number: US202020583A1 Publication Date: 2020-01-16 Application Number: 20/181,603 Filing Date: 2018-07-13 Inventor: Chang, Chih-wei   Tsai, Ming-hsing   Su, Ching-hwanq   Chu, Li-wei   Chao, Yi-hsiang   Hung min hsiu   Li, Ya-huei   Liao, Yu-hsiang   Huang, Hung-yi   Yeh, Kuan-yu   Lin, Kan-ju   Chuang, Chi-hung   Nieh, Chun-wen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
17
KR20190062112A
CONDUCTIVE FEATURE FORMATION AND STRUCTURE
Publication/Patent Number: KR20190062112A Publication Date: 2019-06-05 Application Number: 20180034001 Filing Date: 2018-03-23 Inventor: Lin, Yu Ting   Hung, Min Hsiu   Chang, Cheng Wei   Huang, Huang Yi   Wang, Chun Chieh   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L21/768 Abstract: Generally, the present invention provides example embodiments relating to conductive features, such as metal contacts, vias, lines, and the like, and methods for forming the conductive features. In an embodiment of the method of the present invention, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening part is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening part along sidewalls of the dielectric layer by a same plasma-enhance chemical vapor deposition (PECVD) process.
18
TWI671432B
Conductive feature formation and structure
Publication/Patent Number: TWI671432B Publication Date: 2019-09-11 Application Number: 107116123 Filing Date: 2018-05-11 Inventor: Wang, Chun Chieh   Lin, Yu Ting   Huang, Huang Yi   Chang, Cheng Wei   Hung, Min Hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/205 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
19
TW201925525A
Conductive feature formation and structure
Publication/Patent Number: TW201925525A Publication Date: 2019-07-01 Application Number: 107116123 Filing Date: 2018-05-11 Inventor: Wang, Chun Chieh   Lin, Yu Ting   Huang, Huang Yi   Chang, Cheng Wei   Hung, Min Hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/205 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
20
US2019304833A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2019304833A1 Publication Date: 2019-10-03 Application Number: 15/939,572 Filing Date: 2018-03-29 Inventor: Chen, Pin-wen   Lai, Chia-han   Fu, Mei-hui   Hung min hsiu   Cheng, Ya-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
Total 2 pages