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1
US11054498B2
System and method of configuring an external radar device through high speed reverse data transmission
Publication/Patent Number: US11054498B2 Publication Date: 2021-07-06 Application Number: 16/254,058 Filing Date: 2019-01-22 Inventor: Brett, Maik   Jain, Naveen Kumar   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: G01S7/35 Abstract: System and method of configuring an external radar device through high speed reverse data transmission. In one embodiment, the system includes a radar data processing module for processing radar data received from the external radar device, and a radar configuration management module for generating control data for controlling the external radar device. The system further includes a configurable half-duplex interface, wherein the configurable half-duplex interface, in response to receiving a turnaround command, switches between (1) a configuration for transmitting control data packets to the external radar device via a communication link, and (2) a configuration for receiving radar data packets from the external radar device via the communication link. A receive controller is provided and is configured to receive radar data packets from the external radar device via the communication link and the configurable half-duplex interface, wherein the receive controller is configured to extract radar data from the radar packets for subsequent processing by the radar data processing module. A transmit controller is provided and configured to receive control data from the radar configuration management module, wherein the transmit controller is configured to generate radar control packets comprising the radar control data, and wherein the transmit controller is configured to transmit the radar control packets to the external radar device via the communication link and the configurable half-duplex interface when configured for transmitting data.
2
US2021248598A1
GENERATING EMOJI SEQUENCE IDENTIFICATIONS TO IDENTIFY WALLET ADDRESSES FOR BLOCKCHAIN WALLETS
Publication/Patent Number: US2021248598A1 Publication Date: 2021-08-12 Application Number: 17/168,887 Filing Date: 2021-02-05 Inventor: Jain, Naveen Kumar   Spagni, Riccardo Paolo   Assignee: Emoji ID, LLC   IPC: G06Q20/36 Abstract: Described are methods and systems for generating emoji sequence identifications (IDs) to identify wallet addresses for blockchain wallets, according to some embodiments. In some embodiments, a method for generating an emoji sequence ID for a blockchain wallet includes dividing a predetermined number of bits of a wallet address for the blockchain wallet into a plurality of non-overlapping groups of sequential bits. Then, each group of sequential bits can be converted into a respective emoji ID based on a predetermined list of emojis. The emoji ID for each group of sequential bits can be concatenated into an emoji sequence. The emoji sequence ID identifying the wallet address can be outputted based on the emoji sequence.
3
US10891245B2
Video device and method for embedded data capture on a virtual channel
Publication/Patent Number: US10891245B2 Publication Date: 2021-01-12 Application Number: 15/982,057 Filing Date: 2018-05-17 Inventor: Herrmann, Stephan Matthias   Jain, Naveen Kumar   Jain, Shivali   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: G06F13/16 Abstract: A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.
4
US2021294375A1
SYSTEM AND METHOD OF EARLY TURNAROUND INDICATION FOR A D-PHY COMMUNICATION INTERFACE
Publication/Patent Number: US2021294375A1 Publication Date: 2021-09-23 Application Number: 16/821,954 Filing Date: 2020-03-17 Inventor: Brett, Maik   Jain, Naveen Kumar   Singh, Shreya   Goel, Anshul   Assignee: NXP USA, Inc.   IPC: G06F1/08 Abstract: A communication system including a physical layer circuit, a timer circuit, and a turnaround controller. The physical layer circuit provides an early turnaround indication upon detection of a turnaround command and before completion of the turnaround command. The timer circuit is programmed with a timeout value indicative of a maximum time of a turnaround procedure initiated by the turnaround command. The turnaround controller starts the timer circuit in response to the early turnaround indication. A transmit controller may begin retrieving information to transmit from a memory in response to the early turnaround indication, and may begin transmitting the retrieved information if the turnaround procedure completes before timeout of the timer circuit. The retrieved information may be configuration information for a sensor. The turnaround controller provides an error indication if the timer circuit times out indicating a turnaround error. The error indication enables remedial action to be taken.
5
US2021012118A1
SYSTEM AND METHOD FOR CONTINUOUS OPERATION OF VISION/RADAR SYSTEMS IN PRESENCE OF BIT ERRORS
Publication/Patent Number: US2021012118A1 Publication Date: 2021-01-14 Application Number: 16/505,522 Filing Date: 2019-07-08 Inventor: Bohacik, Pavel   Singh, Shreya   Jain, Nishant   Goel, Anshul   Jain, Shivali   Jain, Naveen Kumar   Assignee: NXP USA, Inc.   IPC: G06K9/00 Abstract: A radar and/or camera system may include a receiver subsystem that receives image and/or radar data from one or more imaging/radar subsystems via multiple data lanes. A vision processor of the system may receive a data stream that includes the image and/or radar data and one or more synchronization signals including a vertical sync signal. The receiver subsystem may include a timing event generator that toggles the vertical sync signal in response to detecting certain timing event errors in order to correct these timing event errors without interrupting normal operation of the system. The receiver subsystem may include sync monitoring circuitry that may detect synchronization errors that occur when synchronization signal pulses received by the receiver subsystem do not match a predefined synchronization pattern within a scan window of predefined length. The system may be reset in response to detection of such synchronization errors.
6
EP3764639A1
SYSTEM AND METHOD FOR CONTINUOUS OPERATION OF VISION/RADAR SYSTEMS IN PRESENCE OF BIT ERRORS
Publication/Patent Number: EP3764639A1 Publication Date: 2021-01-13 Application Number: 20182811.8 Filing Date: 2020-06-29 Inventor: Bohacik, Pavel   Singh, Shreya   Jain, Nishant   Goel, Anshul   Jain, Shivali   Jain, Naveen Kumar   Assignee: NXP USA, Inc.   IPC: H04N7/18 Abstract: A radar and/or camera system may include a receiver subsystem that receives image and/or radar data from one or more imaging/radar subsystems via multiple data lanes. A vision processor of the system may receive a data stream that includes the image and/or radar data and one or more synchronization signals including a vertical sync signal. The receiver subsystem may include a timing event generator that toggles the vertical sync signal in response to detecting certain timing event errors in order to correct these timing event errors without interrupting normal operation of the system. The receiver subsystem may include sync monitoring circuitry that may detect synchronization errors that occur when synchronization signal pulses received by the receiver subsystem do not match a predefined synchronization pattern within a scan window of predefined length. The system may be reset in response to detection of such synchronization errors.
7
US2020233059A1
SYSTEM AND METHOD OF CONFIGURING AN EXTERNAL RADAR DEVICE THROUGH HIGH SPEED REVERSE DATA TRANSMISSION
Publication/Patent Number: US2020233059A1 Publication Date: 2020-07-23 Application Number: 16/254,058 Filing Date: 2019-01-22 Inventor: Brett, Maik   Jain, Naveen Kumar   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: G01S7/35 Abstract: System and method of configuring an external radar device through high speed reverse data transmission. In one embodiment, the system includes a radar data processing module for processing radar data received from the external radar device, and a radar configuration management module for generating control data for controlling the external radar device. The system further includes a configurable half-duplex interface, wherein the configurable half-duplex interface, in response to receiving a turnaround command, switches between (1) a configuration for transmitting control data packets to the external radar device via a communication link, and (2) a configuration for receiving radar data packets from the external radar device via the communication link. A receive controller is provided and is configured to receive radar data packets from the external radar device via the communication link and the configurable half-duplex interface, wherein the receive controller is configured to extract radar data from the radar packets for subsequent processing by the radar data processing module. A transmit controller is provided and configured to receive control data from the radar configuration management module, wherein the transmit controller is configured to generate radar control packets comprising the radar control data, and wherein the transmit controller is configured to transmit the radar control packets to the external radar device via the communication link and the configurable half-duplex interface when configured for transmitting data.
8
EP3696684A1
FAST LINK TURNAROUND USING MIPI D-PHY
Publication/Patent Number: EP3696684A1 Publication Date: 2020-08-19 Application Number: 20151478.3 Filing Date: 2020-01-13 Inventor: Brett, Maik   Jain, Naveen Kumar   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: G06F13/42 Abstract: A system, method, and apparatus are provided for operating a device to receive a first signaling state sequence on a multi-wire interface within a first voltage range to cause the device to transition to a high-speed communication mode for receiving high-speed data on the multi-wire interface within a second, smaller voltage range before returning to a low-power communication mode when the device receives on the multi-wire interface a second sequence of two signaling states within the first voltage range to signal a turnaround command without requiring any additional signaling state within the first voltage range, where the turnaround command enables the device to transmit data from the device over the multi-wire interface by transmitting on the multi-wire interface the first sequence of signaling states within the first voltage range to cause the device to transition to a high-speed communication mode for transmitting data from the device over the multi-wire interface.
9
EP3686627A1
SYSTEM AND METHOD OF CONFIGURING AN EXTERNAL RADAR DEVICE THROUGH HIGH SPEED REVERSE DATA TRANSMISSION
Publication/Patent Number: EP3686627A1 Publication Date: 2020-07-29 Application Number: 20152608.4 Filing Date: 2020-01-20 Inventor: Brett, Maik   Jain, Naveen Kumar   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: G01S13/32 Abstract: System and method of configuring an external radar device through high speed reverse data transmission. In one embodiment, the system includes a radar data processing module for processing radar data received from the external radar device, and a radar configuration management module for generating control data for controlling the external radar device. The system further includes a configurable half-duplex interface, wherein the configurable half-duplex interface, in response to receiving a turnaround command, switches between (1) a configuration for transmitting control data packets to the external radar device via a communication link, and (2) a configuration for receiving radar data packets from the external radar device via the communication link. A receive controller is provided and is configured to receive radar data packets from the external radar device via the communication link and the configurable half-duplex interface, wherein the receive controller is configured to extract radar data from the radar packets for subsequent processing by the radar data processing module. A transmit controller is provided and configured to receive control data from the radar configuration management module, wherein the transmit controller is configured to generate radar control packets comprising the radar control data, and wherein the transmit controller is configured to transmit the radar control packets to the external radar device via the communication link and the configurable half-duplex interface when configured for transmitting data.
10
US10628339B2
Electronic device and method for coherent enable/disable on a virtual data channel
Publication/Patent Number: US10628339B2 Publication Date: 2020-04-21 Application Number: 15/982,090 Filing Date: 2018-05-17 Inventor: Herrmann, Stephan Matthias   Gupta, Gaurav   Jain, Naveen Kumar   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: H04N21/434 Abstract: An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.
11
EP3671720A1
REAL-TIME ON-CHIP DATA TRANSFER SYSTEM
Publication/Patent Number: EP3671720A1 Publication Date: 2020-06-24 Application Number: 19210427.1 Filing Date: 2019-11-20 Inventor: Jain, Naveen Kumar   Fader, Joachim   Singh, Shreya   Jain, Nishant   Goel, Anshul   Assignee: NXP USA, Inc.   IPC: G09G5/00 Abstract: A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver (108), a loopback buffer (110), and a CSI transmitter (112). The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.
12
US10862830B2
Real-time on-chip data transfer system
Publication/Patent Number: US10862830B2 Publication Date: 2020-12-08 Application Number: 16/222,671 Filing Date: 2018-12-17 Inventor: Jain, Naveen Kumar   Fader, Joachim   Singh, Shreya   Jain, Nishant   Goel, Anshul   Assignee: NXP USA, INC.   IPC: H04J3/24 Abstract: A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver, a loopback buffer, and a CSI transmitter. The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.
13
EP3748498A1
SYSTEM AND METHOD FOR SYSTEM FOR ACQUIRING DATA
Publication/Patent Number: EP3748498A1 Publication Date: 2020-12-09 Application Number: 20169685.3 Filing Date: 2020-04-15 Inventor: Singh, Shreya   Brett, Maik   Agarwal, Arpita   Jain, Shivali   Goel, Anshul   Jain, Naveen Kumar   Assignee: NXP USA, Inc.   IPC: G06F9/50 Abstract: A method of acquiring data, a computer program product for implementing the method, a system for acquiring data, and a vehicle including the system. The method includes determining one or more data types and virtual channels required for one or more applications. The method also includes allocating a plurality of circular buffers in memory according to the determined data type(s) and virtual channel(s). One or more of the circular buffers are allocated to safety data lines. The remaining circular buffers are allocated to functional data lines. The method further includes storing at least one functional data line in a circular buffer allocated to functional data lines according to a data type and virtual channel of the functional data line. The method also includes storing at least one safety data line in a circular buffer allocated to safety data lines.
14
US2020379827A1
SYSTEM AND METHOD FOR SYSTEM FOR ACQUIRING DATA
Publication/Patent Number: US2020379827A1 Publication Date: 2020-12-03 Application Number: 16/883,240 Filing Date: 2020-05-26 Inventor: Singh, Shreya   Brett, Maik   Agarwal, Arpita   Jain, Shivali   Goel, Anshul   Jain, Naveen Kumar   Assignee: NXP USA, Inc.   IPC: G06F9/54 Abstract: A method of acquiring data, a computer program product for implementing the method, a system for acquiring data, and a vehicle including the system. The method includes determining one or more data types and virtual channels required for one or more applications. The method also includes allocating a plurality of circular buffers in memory according to the determined data type(s) and virtual channel(s). One or more of the circular buffers are allocated to safety data lines. The remaining circular buffers are allocated to functional data lines. The method further includes storing at least one functional data line in a circular buffer allocated to functional data lines according to a data type and virtual channel of the functional data line. The method also includes storing at least one safety data line in a circular buffer allocated to safety data lines.
15
US2020195589A1
REAL-TIME ON-CHIP DATA TRANSFER SYSTEM
Publication/Patent Number: US2020195589A1 Publication Date: 2020-06-18 Application Number: 16/222,671 Filing Date: 2018-12-17 Inventor: Jain, Naveen Kumar   Fader, Joachim   Singh, Shreya   Jain, Nishant   Goel, Anshul   Assignee: NXP USA, INC.   IPC: H04L12/861 Abstract: A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver, a loopback buffer, and a CSI transmitter. The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.
16
US201957051A1
VIDEO DEVICE AND METHOD FOR EMBEDDED DATA CAPTURE ON A VIRTUAL CHANNEL
Publication/Patent Number: US201957051A1 Publication Date: 2019-02-21 Application Number: 20/181,598 Filing Date: 2018-05-17 Inventor: Singh, Shreya   Herrmann, Stephan Matthias   Jain, Shivali   Jain, Naveen Kumar   Assignee: NXP USA, Inc.   IPC: G06F3/00 Abstract: A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.
17
US2019057046A1
ELECTRONIC DEVICE AND METHOD FOR COHERENT ENABLE/DISABLE ON A VIRTUAL DATA CHANNEL
Publication/Patent Number: US2019057046A1 Publication Date: 2019-02-21 Application Number: 15/982,090 Filing Date: 2018-05-17 Inventor: Herrmann, Stephan Matthias   Gupta, Gaurav   Jain, Naveen Kumar   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: G06F13/16 Abstract: An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.
18
US201957046A1
ELECTRONIC DEVICE AND METHOD FOR COHERENT ENABLE/DISABLE ON A VIRTUAL DATA CHANNEL
Publication/Patent Number: US201957046A1 Publication Date: 2019-02-21 Application Number: 20/181,598 Filing Date: 2018-05-17 Inventor: Gupta, Gaurav   Singh, Shreya   Herrmann, Stephan Matthias   Jain, Naveen Kumar   Assignee: NXP USA, Inc.   IPC: G06F13/16 Abstract: An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.
19
US2019057051A1
VIDEO DEVICE AND METHOD FOR EMBEDDED DATA CAPTURE ON A VIRTUAL CHANNEL
Publication/Patent Number: US2019057051A1 Publication Date: 2019-02-21 Application Number: 15/982,057 Filing Date: 2018-05-17 Inventor: Herrmann, Stephan Matthias   Jain, Naveen Kumar   Jain, Shivali   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: G06F13/16 Abstract: A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.
20
EP3445045A1
VIDEO DEVICE AND METHOD FOR EMBEDDED DATA CAPTURE ON A VIRTUAL CHANNEL
Publication/Patent Number: EP3445045A1 Publication Date: 2019-02-20 Application Number: 17186940.7 Filing Date: 2017-08-18 Inventor: Herrmann, Stephan Matthias   Jain, Naveen Kumar   Jain, Shivali   Singh, Shreya   Assignee: NXP USA, Inc.   IPC: H04N7/18 Abstract: A video device (300) is described that includes: a host processor (210) comprising at least one input video port (306) configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory (330) operably coupled to the host processor and configured to receive and store video data. The host processor (210) is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.
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