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1
US2021020462A1
SUBSTRATE CLEANING APPARATUS AND SUBSTRATE CLEANING METHOD USING THE SAME
Publication/Patent Number: US2021020462A1 Publication Date: 2021-01-21 Application Number: 16/739,409 Filing Date: 2020-01-10 Inventor: Jeong, Jihoon   Park, Mihyun   Ko, Yongsun   Lee, Kwangwook   Lee, Kuntack   Jeon, Hayoung   Cho, Yongjhin   Cha, Jihoon   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/67 Abstract: A substrate cleaning apparatus includes a support inside a chamber to hold a substrate, a first supply source inside the chamber that includes a first nozzle along a first direction and facing an upper surface of the support, the first nozzle to spray polymer and solvent onto the substrate to form a coating, and a second nozzle at an oblique angle to the first direction and facing an edge of the support to inject a hot gas toward the coating to volatilize the solvent, a second supply source inside the chamber and having a third nozzle facing the upper surface of the support to inject a peeling treatment to the coating to peel the coating from the substrate, and a third supply source inside the chamber and facing a lower surface of the support to inject the hot gas to heat a second surface of the substrate.
2
US10622043B2
Multi-pump memory system access circuits for sequentially executing parallel memory operations
Publication/Patent Number: US10622043B2 Publication Date: 2020-04-14 Application Number: 16/126,817 Filing Date: 2018-09-10 Inventor: Nguyen, Hoan Huu   Jeong, Jihoon   Atallah, Francois Ibrahim   Bowman, Keith Alan   Assignee: Qualcomm Incorporated   IPC: G11C8/00 Abstract: Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessible at a corresponding memory address used by memory read and write operations. The memory system includes ports at which a memory read or a memory write operation is received from a processor in each cycle of a processor clock. To increase memory bandwidth of the memory system without increasing the number of access ports of the memory array within the memory system, a double-pump memory system access circuit double-pumps (i.e., time-multiplexes) the access ports of memory array, effectively doubling the number of ports of the memory array. The double-pump memory system access circuit performs sequential accesses to a port of a memory cell in a memory array within a processor clock period.
3
US2020227253A1
SUPERCRITICAL DRYING APPARATUS AND METHOD OF DRYING SUBSTRATE USING THE SAME
Publication/Patent Number: US2020227253A1 Publication Date: 2020-07-16 Application Number: 16/561,078 Filing Date: 2019-09-05 Inventor: Park, Sangjine   Cho, Byung-kwon   Jeong, Jihoon   Kim, Youngtak   Ko, Yongsun   Jeon, Seulgee   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/02 Abstract: A supercritical drying apparatus and a method of drying a substrate, the apparatus including a drying chamber configured to receive a supercritical fluid and to dry a substrate; a chuck in the drying chamber, the chuck being configured to receive the substrate; and a particle remover in the drying chamber, the particle remover being configured to remove dry particles from the substrate by heating the substrate with radiant heat.
4
US2020357462A1
HIGH BANDWIDTH REGISTER FILE CIRCUIT
Publication/Patent Number: US2020357462A1 Publication Date: 2020-11-12 Application Number: 16/406,749 Filing Date: 2019-05-08 Inventor: Nguyen, Hoan Huu   Atallah, Francois Ibrahim   Bowman, Keith Alan   Jeong, Jihoon   Assignee: QUALCOMM Incorporated   IPC: G11C11/419 Abstract: A high bandwidth register file circuit that significantly reduces the shared local read bitline RC delay to enable ultra-high performance PRFs with high port counts. In one example, the register file circuit includes read stack nfets in a multiplexer circuit instead of the memory cell causing the local read bitline RC to be independent of the number of read and write ports of the memory cell.
5
US10825698B2
Substrate drying apparatus, facility of manufacturing semiconductor device, and method of drying substrate
Publication/Patent Number: US10825698B2 Publication Date: 2020-11-03 Application Number: 15/845,236 Filing Date: 2017-12-18 Inventor: Cho, Yong-jhin   Kim, Young-hoo   Jeong, Jihoon   Kim, Yungjun   Lee, Kuntack   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/67 Abstract: Disclosed are a substrate drying apparatus, a facility of manufacturing a semiconductor device, and a method of drying a substrate. The substrate drying apparatus includes a chamber that is configured to dry a substrate at a first temperature, a first reservoir that is configured to store a first supercritical fluid at a second temperature that is less than the first temperature, a second reservoir that is configured to store a second supercritical fluid at a third temperature that is greater than the first temperature, and a supply unit connected between the chamber and the first reservoir and/or second reservoir. The supply unit is configured to supply the chamber with the first supercritical fluid and second supercritical fluid.
6
US2020388484A1
WAFER CLEANING APPARATUS BASED ON LIGHT IRRADIATION AND WAFER CLEANING SYSTEM INCLUDING THE SAME
Publication/Patent Number: US2020388484A1 Publication Date: 2020-12-10 Application Number: 16/744,667 Filing Date: 2020-01-16 Inventor: Cho, Byungkwon   Park, Sangjine   Ko, Yongsun   Jeon, Seulgee   Jeong, Jihoon   Hong, Seongsik   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/02 Abstract: Provided are a wafer cleaning apparatus based on light irradiation capable of effectively cleaning residue on a wafer without damaging the wafer, and a wafer cleaning system including the cleaning apparatus. The wafer cleaning apparatus is configured to clean residue on the wafer by light irradiation and includes: a light irradiation unit configured to irradiate light onto the wafer during the light irradiation; a wafer processing unit configured accommodate the wafer and to control a position of the wafer such that the light is irradiated onto the wafer during the light irradiation; and a cooling unit configured to cool the wafer after the light irradiation has been completed. The light irradiation unit, the wafer processing unit, and the cooling unit are sequentially arranged in a vertical structure with the light irradiation unit above the wafer processing unit and the wafer processing unit above the cooling unit.
7
US2020388327A1
DUAL-MODE HIGH-BANDWIDTH SRAM WITH SELF-TIMED CLOCK CIRCUIT
Publication/Patent Number: US2020388327A1 Publication Date: 2020-12-10 Application Number: 16/431,503 Filing Date: 2019-06-04 Inventor: Nguyen, Hoan Huu   Atallah, Francois Ibrahim   Bowman, Keith Alan   Yingling, Daniel   Jeong, Jihoon   Pu, Yu   Assignee: QUALCOMM Incorporated   IPC: G11C11/417 Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.
8
WO2019051446A1
MULTI-PUMP MEMORY SYSTEM ACCESS CIRCUITS FOR SEQUENTIALLY EXECUTING PARALLEL MEMORY OPERATIONS
Publication/Patent Number: WO2019051446A1 Publication Date: 2019-03-14 Application Number: 2018050347 Filing Date: 2018-09-11 Inventor: Bowman, Keith   Nguyen, Hoan   Jeong, Jihoon   Atallah, Francois   Assignee: Qualcomm Incorporated   IPC: G11C7/10 Abstract: Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessible at a corresponding memory address used by memory read and write operations. The memory system includes ports at which a memory read or a memory write operation is received from a processor in each cycle of a processor clock. To increase memory bandwidth of the memory system without increasing the number of access ports of the memory array within the memory system, a double-pump memory system access circuit double-pumps (i.e., time-multiplexes) the access ports of memory array, effectively doubling the number of ports of the memory array. The double-pump memory system access circuit performs sequential accesses to a port of a memory cell in a memory array within a processor clock period.
9
US2019305501A1
LASER PULSE FILTER AND LASER OUTPUT DEVICE HAVING SAME
Publication/Patent Number: US2019305501A1 Publication Date: 2019-10-03 Application Number: 16/317,034 Filing Date: 2017-07-11 Inventor: Yu, Tae Jun   Jeong, Jihoon   Kim, Tae Shin   Cho, Seryeyohan   Hwang, Seung Jin   Assignee: HANDONG GLOBAL UNIVERCITY INDUSTRYACADEMIC COOPERATION FOUNDATION   IPC: H01S3/00 Abstract: A laser output device includes: a laser oscillator for oscillating a source laser pulse; a pulse extender for temporally extending the source laser pulse oscillated by the laser oscillator; an amplifier for amplifying the laser pulse temporally extended by the pulse extender; the laser pulse filter for filtering a pre-pulse and a post-pulse contained in the amplified laser pulse; and a pulse compressor for temporally compressing the laser pulse which has passed through the laser pulse filter.
10
US2019080737A1
MULTI-PUMP MEMORY SYSTEM ACCESS CIRCUITS FOR SEQUENTIALLY EXECUTING PARALLEL MEMORY OPERATIONS
Publication/Patent Number: US2019080737A1 Publication Date: 2019-03-14 Application Number: 16/126,817 Filing Date: 2018-09-10 Inventor: Nguyen, Hoan Huu   Jeong, Jihoon   Atallah, Francois Ibrahim   Bowman, Keith Alan   Assignee: QUALCOMM Incorporated   IPC: G11C8/16 Abstract: Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessible at a corresponding memory address used by memory read and write operations. The memory system includes ports at which a memory read or a memory write operation is received from a processor in each cycle of a processor clock. To increase memory bandwidth of the memory system without increasing the number of access ports of the memory array within the memory system, a double-pump memory system access circuit double-pumps (i.e., time-multiplexes) the access ports of memory array, effectively doubling the number of ports of the memory array. The double-pump memory system access circuit performs sequential accesses to a port of a memory cell in a memory array within a processor clock period.
11
US201980737A1
MULTI-PUMP MEMORY SYSTEM ACCESS CIRCUITS FOR SEQUENTIALLY EXECUTING PARALLEL MEMORY OPERATIONS
Publication/Patent Number: US201980737A1 Publication Date: 2019-03-14 Application Number: 20/181,612 Filing Date: 2018-09-10 Inventor: Atallah, Francois Ibrahim   Bowman, Keith Alan   Jeong, Jihoon   Nguyen, Hoan Huu   Assignee: QUALCOMM Incorporated   IPC: G11C8/18 Abstract: Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessible at a corresponding memory address used by memory read and write operations. The memory system includes ports at which a memory read or a memory write operation is received from a processor in each cycle of a processor clock. To increase memory bandwidth of the memory system without increasing the number of access ports of the memory array within the memory system, a double-pump memory system access circuit double-pumps (i.e., time-multiplexes) the access ports of memory array, effectively doubling the number of ports of the memory array. The double-pump memory system access circuit performs sequential accesses to a port of a memory cell in a memory array within a processor clock period.
12
US10224084B2
Wordline negative boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods
Publication/Patent Number: US10224084B2 Publication Date: 2019-03-05 Application Number: 15/717,028 Filing Date: 2017-09-27 Inventor: Jeong, Jihoon   Atallah, Francois Ibrahim   Bowman, Keith Alan   Hansquine, David Joseph Winston   Nguyen, Hoan Huu   Assignee: QUALCOMM Incorporated   IPC: G11C11/00 Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of negative wordline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).
13
EP3262650B1
READ-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) READ PORT(S), AND RELATED MEMORY SYSTEMS AND METHODS
Publication/Patent Number: EP3262650B1 Publication Date: 2019-04-24 Application Number: 16704777.8 Filing Date: 2016-02-02 Inventor: Atallah, Francois Ibrahim   Bowman, Keith Alan   Hansquine, David Joseph Winston   Jeong, Jihoon   Nguyen, Hoan Huu   Assignee: Qualcomm Incorporated   IPC: G11C11/412
14
EP3198608B1
REGISTER FILE CIRCUIT AND METHOD FOR IMPROVING THE MINIMUM OPERATING SUPPLY VOLTAGE
Publication/Patent Number: EP3198608B1 Publication Date: 2019-11-06 Application Number: 15750549.6 Filing Date: 2015-08-04 Inventor: Atallah, Francois Ibrahim   Jeong, Jihoon   Bowman, Keith Alan   Kulkarni, Amey Sudhir   Martzloff, Jason Philip   Puckett, Joshua Lance   Assignee: Qualcomm Incorporated   IPC: G11C11/419
15
EP3262644B1
P-TYPE FIELD-EFFECT TRANSISTOR (PFET)-BASED SENSE AMPLIFIERS FOR READING PFET PASS-GATE MEMORY BIT CELLS, AND RELATED MEMORY SYSTEMS AND METHODS
Publication/Patent Number: EP3262644B1 Publication Date: 2019-04-24 Application Number: 16704773.7 Filing Date: 2016-02-02 Inventor: Nguyen, Hoan Huu   Atallah, Francois Ibrahim   Bowman, Keith Alan   Hansquine, David Joseph Winston   Jeong, Jihoon   Assignee: Qualcomm Incorporated   IPC: G11C7/06
16
US10424392B2
Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods
Publication/Patent Number: US10424392B2 Publication Date: 2019-09-24 Application Number: 16/165,549 Filing Date: 2018-10-19 Inventor: Atallah, Francois Ibrahim   Bowman, Keith Alan   Hansquine, David Joseph Winston   Jeong, Jihoon   Nguyen, Hoan Huu   Assignee: QUALCOMM Incorporated   IPC: G11C29/52 Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.
17
EP3467833A1
READ-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) READ PORT(S), AND RELATED MEMORY SYSTEMS AND METHODS
Publication/Patent Number: EP3467833A1 Publication Date: 2019-04-10 Application Number: 18206342.0 Filing Date: 2016-02-02 Inventor: Atallah, Francois Ibrahim   Hansquine, David Joseph Winston   Bowman, Keith Alan   Jeong, Jihoon   Nguyen, Huu Hoan   Assignee: Qualcomm Incorporated   IPC: G11C11/412 Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports
18
US2019057757A1
READ-ASSIST CIRCUITS FOR MEMORY BIT CELLS EMPLOYING A P-TYPE FIELD-EFFECT TRANSISTOR (PFET) READ PORT(S), AND RELATED MEMORY SYSTEMS AND METHODS
Publication/Patent Number: US2019057757A1 Publication Date: 2019-02-21 Application Number: 16/165,549 Filing Date: 2018-10-19 Inventor: Atallah, Francois Ibrahim   Bowman, Keith Alan   Hansquine, David Joseph Winston   Jeong, Jihoon   Nguyen, Hoan Huu   Assignee: QUALCOMM Incorporated   IPC: G11C29/52 Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.
19
US10411266B2
Dry reforming catalyst, method for preparing same, and dry reforming method using corresponding catalyst
Publication/Patent Number: US10411266B2 Publication Date: 2019-09-10 Application Number: 15/542,321 Filing Date: 2015-03-04 Inventor: Nam, Suk Woo   Yoon, Chang Won   Kim, Yeong Cheon   Kim, Yong Min   Han, Jonghee   Yoon, Sung Pil   Ham, Hyung Chul   Jeong, Jihoon   Koh, Seok-keun   Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY   IPC: B01J23/44 Abstract: Provided are: a dry reforming catalyst, in which a noble metal (M) is doped in a nickel yttria stabilized zirconia complex (Ni/YSZ) and an alloy (M-Ni alloy) of the noble metal (M) and nickel is formed at Ni sites on a surface of the nickel yttria stabilized zircona (YSZ); a method for producing the dry reforming catalyst using the noble metal/glucose; and a method for performing dry reforming using the catalyst. The present invention can exhibit a significantly higher dry reforming activity as compared with Ni/YSZ catalysts. Furthermore, the present invention can have an improved long-term performance by suppressing or preventing the deterioration. Furthermore, the preparing method is useful in performing the alloying of noble metal with Ni at Ni sites on the Ni/YSZ surface and can simplify the preparing process, and thus is suitable in mass production.
20
US2018175580A1
LASER AMPLIFICATION DEVICE
Publication/Patent Number: US2018175580A1 Publication Date: 2018-06-21 Application Number: 15/568,792 Filing Date: 2015-04-27 Inventor: Cho, Seryeyohan   Kim, Jeongmoog   Jeong, Jihoon   Yu, Taejun   Assignee: HANDONG GLOBAL UNIVERSITY FOUNDATION   IPC: H01S3/08 Abstract: A laser amplifier capable of achieving a high output by offsetting distortion of an amplified laser beam. The laser amplifier includes: first and second amplification media which amplify a penetrating laser beam; a pre-compensation lens unit which pre-compensates for a laser beam irradiated to the first amplification medium so as to offset a thermal lensing effect generated in the first amplification medium and the second amplification medium; a first polarizing and penetrating mirror inclined to the laser beam irradiated to a front end of the first amplification medium and allowing a laser beam that vibrates in a specific direction to penetrate and reflecting a laser beam that vibrates in another direction; a polarization conversion plate provided at a rear side of the second amplification medium and changing a vibration direction of the laser beam penetrating the second amplification medium; and a first reflection mirror for reflecting a laser beam.
Total 5 pages