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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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Inventor Inventor Assignee Assignee IPC IPC
1
US2021005534A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: US2021005534A1 Publication Date: 2021-01-07 Application Number: 16/968,815 Filing Date: 2019-02-15 Inventor: Sidorov, Victor   Jessenig, Stefan   Parteder, Georg   Assignee: ams AG   IPC: H01L23/48 Abstract: A dielectric layer is arranged on a main surface of a semiconductor substrate, a metal layer providing a contact area is embedded in the dielectric layer, a top metal is arranged on an opposite main surface of the substrate, and an electrically conductive interconnection through the substrate, which comprises a plurality of metallizations arranged in a plurality of via holes, connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer penetrating the substrate.
2
US2021020511A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: US2021020511A1 Publication Date: 2021-01-21 Application Number: 16/980,197 Filing Date: 2019-04-03 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768 Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area.
3
EP3471132B1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3471132B1 Publication Date: 2020-02-26 Application Number: 17196160.0 Filing Date: 2017-10-12 Inventor: Bodner, Thomas   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768
4
EP3756216A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: EP3756216A1 Publication Date: 2020-12-30 Application Number: 19705355.6 Filing Date: 2019-02-15 Inventor: Sidorov, Victor   Jessenig, Stefan   Parteder, Georg   Assignee: AMS AG   IPC: H01L21/768
5
US2020243387A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020243387A1 Publication Date: 2020-07-30 Application Number: 16/754,323 Filing Date: 2018-10-11 Inventor: Bodner, Thomas   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768 Abstract: A method for manufacturing a semiconductor device comprises the steps of providing a semiconductor body with a main plane of extension, and forming a trench in the semiconductor body from a top side of the semiconductor body in a vertical direction which is perpendicular to the main plane of extension of the semiconductor body. The method further comprises the steps of coating inner walls of the trench with an isolation layer, depositing a metallization layer within the trench, and depositing a passivation layer within the trench such that an inner volume of the trench is free of any material, wherein inner surfaces that are adjacent to the inner volume are treated to be hydrophobic at least in places. Furthermore, a semiconductor device is provided.
6
EP3550600B1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND SEMICONDUCTOR DEVICE COMPRISING THE THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3550600B1 Publication Date: 2020-08-05 Application Number: 18165692.7 Filing Date: 2018-04-04 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768
7
EP3471132A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3471132A1 Publication Date: 2019-04-17 Application Number: 17196160.0 Filing Date: 2017-10-12 Inventor: Bodner, Thomas   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768 Abstract: A method for manufacturing a semiconductor device (10) comprises the steps of providing a semiconductor body (11) with a main plane of extension, and forming a trench (12) in the semiconductor body (11) from a top side (13) of the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11). The method further comprises the steps of coating inner walls (14) of the trench (12) with an isolation layer (15), depositing a metallization layer (16) within the trench (12), and depositing a passivation layer (17) within the trench (12) such that an inner volume (18) of the trench (12) is free of any material, wherein inner surfaces (19) that are adjacent to the inner volume (18) are treated to be hydrophobic at least in places. Furthermore, a semiconductor device (10) is provided.
8
WO2019072970A1
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
Publication/Patent Number: WO2019072970A1 Publication Date: 2019-04-18 Application Number: 2018077743 Filing Date: 2018-10-11 Inventor: Schrank, Franz   Jessenig, Stefan   Bodner, Thomas   Assignee: AMS AG   IPC: H01L23/48 Abstract: A method for manufacturing a semiconductor device (10) comprises the steps of providing a semiconductor body (11) with a main plane of extension, and forming a trench (12) in the semiconductor body (11) from a top side (13) of the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11). The method further comprises the steps of coating inner walls (14) of the trench (12) with an isolation layer (15), depositing a metallization layer (16) within the trench (12), and depositing a passivation layer (17) within the trench (12) such that an inner volume (18) of the trench (12) is free of any material, wherein inner surfaces (19) that are adjacent to the inner volume (18) are treated to be hydrophobic at least in places. Furthermore, a semiconductor device (10) is provided.
9
EP3528281A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: EP3528281A1 Publication Date: 2019-08-21 Application Number: 18157371.8 Filing Date: 2018-02-19 Inventor: Sidorov, Victor   Jessenig, Stefan   Parteder, Georg   Assignee: ams AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on a main surface (10) of a semiconductor substrate (1), a metal layer (3) providing a contact area (4) is embedded in the dielectric layer, a top metal (5) is arranged on an opposite main surface (11) of the substrate, and an electrically conductive interconnection (6) through the substrate, which comprises a plurality of metallizations (7) arranged in a plurality of via holes (17), connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer (8) penetrating the substrate.
10
WO2019158706A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND ITS METHOD OF MANUFACTURE
Publication/Patent Number: WO2019158706A1 Publication Date: 2019-08-22 Application Number: 2019053847 Filing Date: 2019-02-15 Inventor: Jessenig, Stefan   Parteder, Georg   Sidorov, Victor   Assignee: AMS AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on a main surface (10) of a semiconductor substrate (1), a metal layer (3) providing a contact area (4) is embedded in the dielectric layer, a top metal (5) is arranged on an opposite main surface (11) of the substrate,and an electrically conductive interconnection (6) through the substrate, which comprises a plurality of metallizations (7) arranged in a plurality of via holes (17), connects the contact area with the top metal. The plurality of metallizations is surrounded by an insulating layer (8) penetrating the substrate.
11
WO2019193067A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: WO2019193067A1 Publication Date: 2019-10-10 Application Number: 2019058430 Filing Date: 2019-04-03 Inventor: Schrank, Franz   Kraft, Jochen   Jessenig, Stefan   Siegert, JÖrg   Parteder, Georg   Assignee: AMS AG   IPC: H01L23/48 Abstract: A substrate (1) is provided with a dielectric (2), a metal layer (3) embedded in the dielectric, and a metallic layer (4) arranged on the metal layer between the substrate and the metal layer. A via hole (9) is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer (11) is applied in the via hole and removed from above a contact area (10) of the metal layer, and the metallic layer is completely removed from the contact area (10). A metallization (12) is applied in the via hole on the contact area.
12
EP3550600A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3550600A1 Publication Date: 2019-10-09 Application Number: 18165692.7 Filing Date: 2018-04-04 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768 Abstract: A substrate (1) is provided with a dielectric (2), a metal layer (3) embedded in the dielectric, and a metallic layer (4) arranged on the metal layer between the substrate and the metal layer. A via hole (9) is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer (11) is applied in the via hole and removed from above a contact area (10) of the metal layer, and the metallic layer is completely removed from the contact area (10). A metallization (12) is applied in the via hole on the contact area.
13
US10374114B2
Lateral single-photon avalanche diode and method of producing a lateral single-photon avalanche diode
Publication/Patent Number: US10374114B2 Publication Date: 2019-08-06 Application Number: 14/777,484 Filing Date: 2014-03-11 Inventor: Teva, Jordi   Roger, Frederic   Stueckler, Ewald   Jessenig, Stefan   Minixhofer, Rainer   Wachmann, Ewald   Schrems, Martin   Koppitsch, Guenther   Assignee: ams AG   IPC: H01L31/107 Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.
14
EP3312874A1
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3312874A1 Publication Date: 2018-04-25 Application Number: 16194866.6 Filing Date: 2016-10-20 Inventor: Kraft, Jochen   Parteder, Georg   Jessenig, Stefan   Schrank, Franz   Assignee: ams AG   IPC: H01L21/768 Abstract: The method of forming a through-substrate via comprises providing a substrate (1) with a dielectric (2) arranged on the substrate (1) and with a metal layer (3) embedded in the dielectric (2), forming a via hole (9) penetrating the substrate (1), removing the dielectric (2) from above the metal layer (3), so that the via hole (9) reaches the metal layer (3), and a contact area (10) of the metal layer (3) is exposed inside the via hole (9), applying an insulation layer (11) in the via hole (9), removing the insulation layer (11) from above the metal layer (3), and applying a metallization (12) in the via hole (9), the metallization (12) contacting a contact area (10) of the metal layer (3) and being insulated from the substrate (1) by the insulation layer (11).
15
EP2973746A2
LATERAL SINGLE-PHOTON AVALANCHE DIODE AND THEIR MANUFACTURING METHOD
Publication/Patent Number: EP2973746A2 Publication Date: 2016-01-20 Application Number: 14709629.1 Filing Date: 2014-03-11 Inventor: Teva, Jordi   Roger, Frederic   StÜckler, Ewald   Jessenig, Stefan   Minixhofer, Rainer   Wachmann, Ewald   Schrems, Martin   Koppitsch, Günther   Assignee: AMS AG   IPC: H01L31/107
16
US2016035929A1
LATERAL SINGLE-PHOTON AVALANCHE DIODE AND METHOD OF PRODUCING A LATERAL SINGLE-PHOTON AVALANCHE DIODE
Publication/Patent Number: US2016035929A1 Publication Date: 2016-02-04 Application Number: 14/777,484 Filing Date: 2014-03-11 Inventor: Teva, Jordi   Roger, Frederic   Stueckler, Ewald   Jessenig, Stefan   Minixhofer, Rainer   Wachmann, Ewald   Schrems, Martin   Koppitsch, Guenther   Assignee: AMS AG   IPC: H01L31/107 Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.
17
DE102011010362B4
Semiconductor device has planar conductor that is formed on insulation layer in opposite side of substrate
Publication/Patent Number: DE102011010362B4 Publication Date: 2014-07-10 Application Number: 102011010362 Filing Date: 2011-02-04 Inventor: Kraft, Jochen Dr   Jessenig, Stefan   Schindler, Stefan   LÖffler, Bernhard   Assignee: Austriamicrosystems AG   IPC: H01L21/28 Abstract: The device has a semiconductor substrate (1) that is provided with an insulation layer (13)
18
WO2014140000A3
LATERAL SINGLE-PHOTON AVALANCHE DIODE AND THEIR MANUFACTURING METHOD
Publication/Patent Number: WO2014140000A3 Publication Date: 2014-12-04 Application Number: 2014054684 Filing Date: 2014-03-11 Inventor: Schrems, Martin   Minixhofer, Rainer   Wachmann, Ewald   Roger, Frederic   Jessenig, Stefan   StÜckler, Ewald   Koppitsch, GÜnther   Teva, Jordi   Assignee: AMS AG   IPC: H01L31/0224 Abstract: The lateral single-photon avalanche diode comprises a semiconductor body (1
19
WO2014140000A2
LATERAL SINGLE-PHOTON AVALANCHE DIODE AND THEIR MANUFACTURING METHOD
Publication/Patent Number: WO2014140000A2 Publication Date: 2014-09-18 Application Number: 2014054684 Filing Date: 2014-03-11 Inventor: Schrems, Martin   Minixhofer, Rainer   Wachmann, Ewald   Roger, Frederic   Jessenig, Stefan   StÜckler, Ewald   Koppitsch, GÜnther   Teva, Jordi   Assignee: AMS AG   IPC: H01L31/0224 Abstract: The lateral single-photon avalanche diode comprises a semiconductor body (1
20
US8884442B2
Method for producing a semiconductor component with a through-contact and semiconductor component with through-contact
Publication/Patent Number: US8884442B2 Publication Date: 2014-11-11 Application Number: 13/820,998 Filing Date: 2011-08-09 Inventor: Kraft, Jochen   Jessenig, Stefan   Koppitsch, Günther   Schrank, Franz   Teva, Jordi   Löffler, Bernhard   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/48 Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed, and a contact area of a connection metal plane (3) that faces the substrate is exposed in the contact hole. A metallization (11) is applied, which forms a connection contact (12) on the contact area, a through-contact (13) in the contact hole and a connection contact (20) on a contact area facing away from the substrate and/or on a vertical conductive connection (15) of the upper metal plane (24).
Total 2 pages