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1 | EP2889901B1 |
Semiconductor device with through-substrate via and corresponding method
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Publication/Patent Number: EP2889901B1 | Publication Date: 2021-02-03 | Application Number: 13199683.7 | Filing Date: 2013-12-27 | Inventor： Schrank, Franz Carniello, Sara Enichlmair, Hubert Kraft, Jochen Löffler, Bernhard Holzhaider, Rainer | Assignee: ams AG | IPC: H01L21/768 | ||||
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2 | US2021020511A1 |
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND A SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
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Publication/Patent Number: US2021020511A1 | Publication Date: 2021-01-21 | Application Number: 16/980,197 | Filing Date: 2019-04-03 | Inventor： Kraft, Jochen Parteder, Georg Jessenig, Stefan Schrank, Franz Siegert, Jörg | Assignee: ams AG | IPC: H01L21/768 | Abstract: A substrate is provided with a dielectric, a metal layer embedded in the dielectric, and a metallic layer arranged on the metal layer between the substrate and the metal layer. A via hole is formed in the substrate and in a region of the dielectric that is between the substrate and the metal layer. An insulation layer is applied in the via hole and removed from above a contact area of the metal layer, and the metallic layer is completely removed from the contact area. A metallization is applied in the via hole on the contact area. | |||
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3 | US10684412B2 |
Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device
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Publication/Patent Number: US10684412B2 | Publication Date: 2020-06-16 | Application Number: 15/757,645 | Filing Date: 2016-08-25 | Inventor： Kraft, Jochen Siegert, Joerg | Assignee: ams AG | IPC: G02B6/12 | Abstract: A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers. | |||
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4 | US2020284727A1 |
CHEMICAL SENSING DEVICE USING FLUORESCENT SENSING MATERIAL
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Publication/Patent Number: US2020284727A1 | Publication Date: 2020-09-10 | Application Number: 16/766,179 | Filing Date: 2018-11-28 | Inventor： Sagmeister, Martin Sidorov, Victor Kraft, Jochen | Assignee: ams AG | IPC: G01N21/64 | Abstract: The chemical sensing device comprises a substrate of semiconductor material, integrated circuit components and a photodetector formed in the substrate, a dielectric on the substrate, a wiring in the dielectric, and a source of electromagnetic radiation, a waveguide and a fluorescent sensor layer arranged in or above the dielectric. A portion of the waveguide is arranged to allow the electromagnetic radiation emitted by the source of electromagnetic radiation to be coupled into the waveguide. A further portion of the waveguide is arranged between the photodetector and the fluorescent sensor layer. | |||
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5 | EP3460835B1 |
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
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Publication/Patent Number: EP3460835B1 | Publication Date: 2020-04-01 | Application Number: 17192105.9 | Filing Date: 2017-09-20 | Inventor： Parteder, Georg Kraft, Jochen Coppeta, Raffaele | Assignee: ams AG | IPC: H01L21/768 | ||||
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6 | US2020020611A1 |
Semiconductor Device
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Publication/Patent Number: US2020020611A1 | Publication Date: 2020-01-16 | Application Number: 16/483,884 | Filing Date: 2018-02-14 | Inventor： Kraft, Jochen Parteder, Georg Singulani, Anderson Coppeta, Raffaele Schrank, Franz | Assignee: ams AG | IPC: H01L23/48 | Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction. | |||
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7 | US202020611A1 |
Semiconductor Device
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Publication/Patent Number: US202020611A1 | Publication Date: 2020-01-16 | Application Number: 20/181,648 | Filing Date: 2018-02-14 | Inventor： Singulani, Anderson Kraft, Jochen Parteder, Georg Coppeta, Raffaele Schrank, Franz | Assignee: ams AG | IPC: H01L23/528 | Abstract: A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction. | |||
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8 | EP3628990A1 |
INTEGRATED OPTICAL TRANSDUCER AND METHOD FOR DETECTING DYNAMIC PRESSURE CHANGES
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Publication/Patent Number: EP3628990A1 | Publication Date: 2020-04-01 | Application Number: 18196899.1 | Filing Date: 2018-09-26 | Inventor： Stojanovic, Goran Steele, Colin Hofrichter, Jens Lazar, Catalin Kraft, Jochen | Assignee: ams International AG | IPC: G01L9/00 | Abstract: An integrated optical transducer (1) for detecting dynamic pressure changes comprises a micro-electro-mechanical system, MEMS, die (10) having a MEMS diaphragm (11) with a first side (12) exposed to the dynamic pressure changes and a second side (13), and an application-specific integrated circuit, ASIC, die (20) having an optical interferometer assembly. The interferometer assembly comprises a beam splitting element (21) for receiving a source beam (30) from a light source (23) and for splitting the source beam (30) into a probe beam (31) in a first beam path and a reference beam (32) in a second beam path, a beam combining element (22) for combining the probe beam (31) with the reference beam (32) to a superposition beam (33), and a detector (24) configured to generate an electronic interference signal depending on the superposition beam (33). The MEMS die (10) is arranged with respect to the ASIC die (20) such that a gap is formed between the second side (12) of the diaphragm and the ASIC die (20), with the gap defining a cavity (14) and having a gap height. The first beam path of the probe beam (31) comprises coupling into the cavity (14), reflection off of a deflection point or a deflection surface (16) of the diaphragm (11) and coupling out of the cavity (14). | |||
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9 | EP3550600B1 |
METHOD OF FORMING A THROUGH-SUBSTRATE VIA AND SEMICONDUCTOR DEVICE COMPRISING THE THROUGH-SUBSTRATE VIA
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Publication/Patent Number: EP3550600B1 | Publication Date: 2020-08-05 | Application Number: 18165692.7 | Filing Date: 2018-04-04 | Inventor： Kraft, Jochen Parteder, Georg Jessenig, Stefan Schrank, Franz Siegert, Jörg | Assignee: ams AG | IPC: H01L21/768 | ||||
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10 | US201925505A1 |
SEMICONDUCTOR DEVICE WITH PHOTONIC AND ELECTRONIC FUNCTIONALITY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
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Publication/Patent Number: US201925505A1 | Publication Date: 2019-01-24 | Application Number: 20/161,575 | Filing Date: 2016-08-25 | Inventor： Siegert, Joerg Kraft, Jochen | Assignee: ams AG | IPC: H01L23/522 | Abstract: A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers. | |||
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11 | US2019025505A1 |
SEMICONDUCTOR DEVICE WITH PHOTONIC AND ELECTRONIC FUNCTIONALITY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
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Publication/Patent Number: US2019025505A1 | Publication Date: 2019-01-24 | Application Number: 15/757,645 | Filing Date: 2016-08-25 | Inventor： Kraft, Jochen Siegert, Joerg | Assignee: ams AG | IPC: G02B6/12 | Abstract: A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers. | |||
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12 | EP3141941B1 |
SEMICONDUCTOR DEVICE WITH PHOTONIC AND ELECTRONIC FUNCTIONALITY AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
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Publication/Patent Number: EP3141941B1 | Publication Date: 2019-11-27 | Application Number: 15184698.7 | Filing Date: 2015-09-10 | Inventor： Kraft, Jochen Siegert, Jörg | Assignee: ams AG | IPC: G02B6/43 | ||||
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13 | TW201916249A |
Method for manufacturing a semiconductor device and semiconductor device
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Publication/Patent Number: TW201916249A | Publication Date: 2019-04-16 | Application Number: 107130141 | Filing Date: 2018-08-29 | Inventor： Kraft, Jochen Parteder, Georg Coppeta, Raffaele | Assignee: AMS AG | IPC: H01L21/76 | Abstract: A method for manufacturing a semiconductor device (10) is provided. The method comprises the steps of providing a semiconductor body (11), forming a trench (12) in the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11), and coating inner walls (13) of the trench (12) with an isolation layer (14). The method further comprises the steps of coating the isolation layer (14) at the inner walls (13) with a metallization layer (15), coating a top side (16) of the semiconductor body (11), at which the trench (12) is formed, at least partially with an electrically conductive contact layer (17), where the contact layer (17) is electrically connected with the metallization layer (15), coating the top side (16) of the semiconductor body (11) at least partially and the trench (12) with a capping layer (24), and forming a contact pad (18) at the top side (16) of the semiconductor body (11) by removing the contact layer (17) and the capping layer (24) at least partially. Furthermore, a semiconductor device (10) is provided. | |||
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14 | EP2860560B1 |
Semiconductor device with optical and electrical vias
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Publication/Patent Number: EP2860560B1 | Publication Date: 2019-07-24 | Application Number: 13188483.5 | Filing Date: 2013-10-14 | Inventor： Kraft, Jochen Rohracher, Karl Teva, Jordi | Assignee: ams AG | IPC: G02B6/42 | ||||
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15 | EP2881983B1 |
Interposer-chip-arrangement for dense packaging of chips
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Publication/Patent Number: EP2881983B1 | Publication Date: 2019-09-18 | Application Number: 13198854.5 | Filing Date: 2013-12-20 | Inventor： Kraft, Jochen Schrank, Franz Schrems, Martin | Assignee: ams AG | IPC: H01L21/60 | ||||
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16 | WO2019057436A1 |
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
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Publication/Patent Number: WO2019057436A1 | Publication Date: 2019-03-28 | Application Number: 2018072767 | Filing Date: 2018-08-23 | Inventor： Kraft, Jochen Parteder, Georg Coppeta, Raffaele | Assignee: AMS AG | IPC: H01L23/48 | Abstract: A method for manufacturing a semiconductor device (10) is provided. The method comprises the steps of providing a semiconductor body (11), forming a trench (12) in the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11), and coating inner walls (13) of the trench (12) with an isolation layer (14). The method further comprises the steps of coating the isolation layer (14) at the inner walls (13) with a metallization layer (15), coating a top side (16) of the semiconductor body (11), at which the trench (12) is formed, at least partially with an electrically conductive contact layer (17), where the contact layer (17) is electrically connected with the metallization layer (15), coating the top side (16) of the semiconductor body (11) at least partially and the trench (12) with a capping layer (24), and forming a contact pad (18) at the top side (16) of the semiconductor body (11) by removing the contact layer (17) and the capping layer (24) at least partially. Furthermore, a semiconductor device (10) is provided. | |||
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17 | US10340254B2 |
Method of producing an interposer-chip-arrangement for dense packaging of chips
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Publication/Patent Number: US10340254B2 | Publication Date: 2019-07-02 | Application Number: 15/726,905 | Filing Date: 2017-10-06 | Inventor： Kraft, Jochen Schrems, Martin Schrank, Franz | Assignee: ams AG | IPC: H01L21/00 | Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection. | |||
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18 | EP3492909A1 |
CHEMICAL SENSING DEVICE USING FLUORESCENT SENSING MATERIAL
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Publication/Patent Number: EP3492909A1 | Publication Date: 2019-06-05 | Application Number: 17204932.2 | Filing Date: 2017-12-01 | Inventor： Sagmeister, Martin Sidorov, Victor Kraft, Jochen | Assignee: ams AG | IPC: G01N21/77 | Abstract: The chemical sensing device comprises a substrate (1) of semiconductor material, integrated circuit components (2) and a photodetector (3) formed in the substrate (1), a dielectric (4) on the substrate (1), a wiring (5) in the dielectric, and a source of electromagnetic radiation (6), a waveguide (9) and a fluorescent sensor layer (14) arranged in or above the dielectric. A portion of the waveguide is arranged to allow the electromagnetic radiation emitted by the source of electromagnetic radiation to be coupled into the waveguide. A further portion of the waveguide is arranged between the photodetector and the fluorescent sensor layer. | |||
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19 | WO2019106023A1 |
CHEMICAL SENSING DEVICE USING FLUORESCENT SENSING MATERIAL
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Publication/Patent Number: WO2019106023A1 | Publication Date: 2019-06-06 | Application Number: 2018082867 | Filing Date: 2018-11-28 | Inventor： Kraft, Jochen Sagmeister, Martin Sidorov, Victor | Assignee: AMS AG | IPC: G02B6/43 | Abstract: The chemical sensing device comprises a substrate (1) of semiconductor material, integrated circuit components (2) and a photodetector (3) formed in the substrate (1), a dielectric (4) on the substrate (1), a wiring (5) in the dielectric, and a source of electromagnetic radiation (6), a waveguide (9) and a fluorescent sensor layer (14) arranged in or above the dielectric. A portion of the waveguide is arranged to allow the electromagnetic radiation emitted by the source of electromagnetic radiation to be coupled into the waveguide. A further portion of the waveguide is arranged between the photodetector and the fluorescent sensor layer. | |||
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20 | EP3460835A1 |
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
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Publication/Patent Number: EP3460835A1 | Publication Date: 2019-03-27 | Application Number: 17192105.9 | Filing Date: 2017-09-20 | Inventor： Parteder, Georg Kraft, Jochen Coppeta, Raffaele | Assignee: ams AG | IPC: H01L21/768 | Abstract: A method for manufacturing a semiconductor device (10) is provided. The method comprises the steps of providing a semiconductor body (11), forming a trench (12) in the semiconductor body (11) in a vertical direction (z) which is perpendicular to the main plane of extension of the semiconductor body (11), and coating inner walls (13) of the trench (12) with an isolation layer (14). The method further comprises the steps of coating the isolation layer (14) at the inner walls (13) with a metallization layer (15), coating a top side (16) of the semiconductor body (11), at which the trench (12) is formed, at least partially with an electrically conductive contact layer (17), where the contact layer (17) is electrically connected with the metallization layer (15), coating the top side (16) of the semiconductor body (11) at least partially and the trench (12) with a capping layer (24), and forming a contact pad (18) at the top side (16) of the semiconductor body (11) by removing the contact layer (17) and the capping layer (24) at least partially. Furthermore, a semiconductor device (10) is provided. |
3.Current Quota