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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2020064396A1
METHOD AND SYSTEM FOR WAFER-LEVEL TESTING
Publication/Patent Number: US2020064396A1 Publication Date: 2020-02-27 Application Number: 16/522,551 Filing Date: 2019-07-25 Inventor: He, Jun   Lin, Yu-ting   Lin, Wei-hsun   Kuo yung liang   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: G01R31/28 Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
2
US8248091B2
Universal array type probe card design for semiconductor device testing
Publication/Patent Number: US8248091B2 Publication Date: 2012-08-21 Application Number: 11/551,558 Filing Date: 2006-10-20 Inventor: Cheng, Hsu Ming   Kuo yung liang   Lee, Pi-huang   Luh, Ann   Hwang, Frank   Wu, Wen-hung   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R31/20 Abstract: A universal system for testing different semiconductor devices provides a probe head with a probe pattern that may be used to test different test patterns formed on different semiconductor devices. Each of a plurality of bumps or pads of the test pattern contacts a corresponding probe of the probe head to enable the semiconductor device to be tested. The universal probe head may additionally or alternatively include a substrate design on the probe head that provides a pattern on the substrate of the probe head that may be used in conjunction with different patterns formed on a plurality of different printed circuit boards for testing different semiconductor devices.
3
TWI341005B
Semiconductor die and package structure
Publication/Patent Number: TWI341005B Publication Date: 2011-04-21 Application Number: 96128172 Filing Date: 2007-08-01 Inventor: Hsu, Ming Cheng   Luo, Wen Liang   Kuo, Yung Liang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/66 Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface
4
TWI335061B
Methods for fabricating semiconductor structures and probing dies
Publication/Patent Number: TWI335061B Publication Date: 2010-12-21 Application Number: 96111280 Filing Date: 2007-03-30 Inventor: Hsu, Ming Cheng   Luo, Wen Liang   Kuo, Yung Liang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R31/26 Abstract: A method for forming a semiconductor structures includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate
5
US7781235B2
Chip-probing and bumping solutions for stacked dies having through-silicon vias
Publication/Patent Number: US7781235B2 Publication Date: 2010-08-24 Application Number: 11/644,397 Filing Date: 2006-12-21 Inventor: Luo, Wen-liang   Kuo yung liang   Cheng, Hsu Ming   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/66 Abstract: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.
6
US7598523B2
Test structures for stacking dies having through-silicon vias
Publication/Patent Number: US7598523B2 Publication Date: 2009-10-06 Application Number: 11/725,403 Filing Date: 2007-03-19 Inventor: Luo, Wen-liang   Kuo yung liang   Cheng, Hsu Ming   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/10 Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.
7
TW200839915A
Semiconductor die and package structure
Publication/Patent Number: TW200839915A Publication Date: 2008-10-01 Application Number: 96128172 Filing Date: 2007-08-01 Inventor: Hsu, Ming Cheng   Luo, Wen Liang   Kuo, Yung Liang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/66 Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface
8
TW200828465A
Methods for fabricating semiconductor structures and probing dies
Publication/Patent Number: TW200828465A Publication Date: 2008-07-01 Application Number: 96111280 Filing Date: 2007-03-30 Inventor: Hsu, Ming Cheng   Luo, Wen Liang   Kuo, Yung Liang   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01R31/26 Abstract: A method for forming a semiconductor structures includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate
9
US2008153187A1
Chip-probing and bumping solutions for stacked dies having through-silicon vias
Publication/Patent Number: US2008153187A1 Publication Date: 2008-06-26 Application Number: 11/644,397 Filing Date: 2006-12-21 Inventor: Luo, Wen-liang   Kuo yung liang   Cheng, Hsu Ming   Assignee: Luo, Wen-Liang   Kuo yung liang   Cheng, Hsu Ming   IPC: H01L21/66 Abstract: A method of forming a semiconductor structure includes providing a stack structure having a first side and a second side opposite the first side. The stack structure includes a bottom wafer comprising a substrate; a plurality of through-silicon vias in the substrate; and a plurality of under bump metallurgies (UBMs) connected to the plurality of through-silicon vias, wherein the UBMs are on the first side of the stack structure. The method further includes attaching a handling wafer on the second side of the stack structure; performing a chip probing process; and removing the handling wafer from the stack structure.
10
US2008272372A1
Test structures for stacking dies having through-silicon vias
Publication/Patent Number: US2008272372A1 Publication Date: 2008-11-06 Application Number: 11/725,403 Filing Date: 2007-03-19 Inventor: Luo, Wen-liang   Kuo yung liang   Cheng, Hsu Ming   Assignee: Luo, Wen-Liang   Kuo yung liang   Cheng, Hsu Ming   IPC: H01L29/10 Abstract: A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads.