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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
EP2889901B1
Semiconductor device with through-substrate via and corresponding method
Publication/Patent Number: EP2889901B1 Publication Date: 2021-02-03 Application Number: 13199683.7 Filing Date: 2013-12-27 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Löffler, Bernhard   Holzhaider, Rainer   Assignee: ams AG   IPC: H01L21/768
2
EP2802004B1
Method of structuring a device layer of a recessed semiconductor device and recessed semiconductor device comprising a structured device layer
Publication/Patent Number: EP2802004B1 Publication Date: 2020-11-04 Application Number: 13167088.7 Filing Date: 2013-05-08 Inventor: Löffler, Bernhard   Schrems, Martin   Assignee: ams AG   IPC: H01L21/311
3
EP3671823A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA
Publication/Patent Number: EP3671823A1 Publication Date: 2020-06-24 Application Number: 18215468.2 Filing Date: 2018-12-21 Inventor: Löffler, Bernhard   Bodner, Thomas   Siegert, Jörg   Assignee: ams AG   IPC: H01L21/768 Abstract: An intermetal dielectric (3) and metal layers (4) embedded in the intermetal dielectric (3) are arranged on a substrate (1) of semiconductor material. A via hole (7) is formed in the substrate, and a metallization (9) contacting a contact area (4*) of one of the metal layers (4') is applied in the via hole. The metallization (9), the metal layer (4') comprising the contact area (4*) and the intermetal dielectric (3) are partially removed at the bottom of the via hole in order to form a hole (16) penetrating the intermetal dielectric and extending the via hole. A continuous passivation (12) is arranged on sidewalls within the via hole (7) and the hole (16), and the metallization (9) contacts the contact area (4*) around the hole (16). Thus the presence of a thin membrane of layers, which is usually formed at the bottom of a hollow through-substrate via, is avoided.
4
EP3754730A1
SEMICONDUCTOR DEVICE FOR INFRARED DETECTION, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE FOR INFRARED DETECTION AND INFRARED DETECTOR
Publication/Patent Number: EP3754730A1 Publication Date: 2020-12-23 Application Number: 19180949.0 Filing Date: 2019-06-18 Inventor: Meinhardt, Gerald   Jonak-auer, Ingrid   Fasching, Gernot   Löffler, Bernhard   Assignee: ams AG   IPC: H01L31/109 Abstract: A semiconductor device for infrared detection comprises a stack of a first semiconductor layer (1), a second semiconductor layer (2) and an optical coupling layer (3). The first semiconductor layer (1) has a first type of conductivity and the second semiconductor layer (2) has a second type of conductivity. The optical coupling layer (3) comprises an optical coupler (31) and at least a first lateral absorber region (32). The optical coupler (31) is configured to deflect incident light towards the first lateral absorber region (32). The first lateral absorber region (32) comprises an absorber material with a bandgap Eg in the infrared, IR.
5
WO2019101577A1
NEAR-INFRARED PHOTODETECTOR SEMICONDUCTOR DEVICE
Publication/Patent Number: WO2019101577A1 Publication Date: 2019-05-31 Application Number: 2018081086 Filing Date: 2018-11-13 Inventor: Meinhardt, Gerald   Jonak-auer, Ingrid   LÖffler, Bernhard   Assignee: AMS AG   IPC: H01L31/028 Abstract: The near-infrared photodetector semiconductor device comprises a semiconductor layer (1) of a first type of conductivity with a main surface (10), a trench or a plurality of trenches (2) in the semiconductor layer at the main surface, a SiGe alloy layer (3) in the trench or the plurality of trenches, and an electrically conductive filling material of a second type of conductivity in the trench or the plurality of trenches, the second type of conductivity being opposite to the first type of conductivity.
6
EP3490000A1
NEAR-INFRARED PHOTODETECTOR SEMICONDUCTOR DEVICE
Publication/Patent Number: EP3490000A1 Publication Date: 2019-05-29 Application Number: 17203572.7 Filing Date: 2017-11-24 Inventor: Jonak-auer, Ingrid   Meinhardt, Gerald   Löffler, Bernhard   Assignee: ams AG   IPC: H01L27/146 Abstract: The near-infrared photodetector semiconductor device comprises a semiconductor layer (1) of a first type of conductivity with a main surface (10), a trench or a plurality of trenches (2) in the semiconductor layer at the main surface, a SiGe alloy layer (3) in the trench or the plurality of trenches, and an electrically conductive filling material of a second type of conductivity in the trench or the plurality of trenches, the second type of conductivity being opposite to the first type of conductivity.
7
EP2648214B1
Methods of producing a semiconductor device with a through-substrate via
Publication/Patent Number: EP2648214B1 Publication Date: 2019-06-12 Application Number: 12163391.1 Filing Date: 2012-04-05 Inventor: Löffler, Bernhard   Rohracher, Karl   Schrank, Franz   Siegert, Jörg   Kraft, Jochen   Assignee: ams AG   IPC: H01L21/768
8
EP2790211B1
Method of producing a through-substrate via in a semiconductor device and semiconductor device comprising a through-substrate via
Publication/Patent Number: EP2790211B1 Publication Date: 2018-06-20 Application Number: 13163167.3 Filing Date: 2013-04-10 Inventor: Kraft, Jochen   Löffler, Bernhard   Koppitsch, Günther   Rohracher, Karl   Assignee: AMS AG   IPC: H01L21/768 Abstract: The method comprises the steps of arranging an intermetal dielectric (2) on or above a main surface (10) of a semiconductor body (1) and at least one metal layer (5, 5') in the intermetal dielectric, and forming a via opening (3) from a rear surface (11) towards the metal layer. A stop layer (4) of electrically conductive material is arranged at the metal layer between the metal layer and the semiconductor body, and the via opening is formed at least up to the stop layer but not into the metal layer. The semiconductor device has a stop layer (4) between a section (5) of the metal layer and a metallization (19) of a through-substrate via that is arranged in the via opening, and an electrically conductive liner (6, 6') between the metal layer and the semiconductor body.
9
DE102007018098B4
Verfahren zum Herstellen eines Halbleiterkörpers mit einem Graben und Halbleiterkörper mit einem Graben
Title (English): Fabrication of semiconductors with trenches and semiconductors
Publication/Patent Number: DE102007018098B4 Publication Date: 2016-06-16 Application Number: 102007018098 Filing Date: 2007-04-17 Inventor: Knaipp, Martin Dr   LÖffler, Bernhard   Assignee: Austriamicrosystems AG   IPC: H01L21/76 Abstract: Verfahren zum Herstellen eines Halbleiterkörpers mit einem Graben
10
EP3012857A1
Method of producing an opening with smooth vertical sidewall in a semiconductor substrate
Publication/Patent Number: EP3012857A1 Publication Date: 2016-04-27 Application Number: 14189757.9 Filing Date: 2014-10-21 Inventor: Koppitsch, Günther   Löffler, Bernhard   Assignee: ams AG   IPC: H01L21/3065 Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.
11
WO2016062614A1
METHOD OF PRODUCING AN OPENING WITH SMOOTH VERTICAL SIDEWALL IN A SEMICONDUCTOR SUBSTRATE
Publication/Patent Number: WO2016062614A1 Publication Date: 2016-04-28 Application Number: 2015073923 Filing Date: 2015-10-15 Inventor: LÖffler, Bernhard   Koppitsch, GÜnther   Assignee: AMS AG   IPC: H01L21/3065 Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles
12
WO2015097002A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND CORRESPONDING METHOD OF MANUFACTURE
Publication/Patent Number: WO2015097002A1 Publication Date: 2015-07-02 Application Number: 2014077587 Filing Date: 2014-12-12 Inventor: Schrank, Franz   Kraft, Jochen   Enichlmair, Hubert   Carniello, Sara   LÖffler, Bernhard   Holzhaider, Rainer   Assignee: AMS AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1)
13
EP2889901A1
Semiconductor device with through-substrate via and method of producing a semiconductor device with through-substrate via
Publication/Patent Number: EP2889901A1 Publication Date: 2015-07-01 Application Number: 13199683.7 Filing Date: 2013-12-27 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Löffler, Bernhard   Holzhaider, Rainer   Assignee: ams AG   IPC: H01L21/768 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.
14
EP2802004A1
Method of structuring a device layer of a recessed semiconductor device and recessed semiconductor device comprising a structured device layer
Publication/Patent Number: EP2802004A1 Publication Date: 2014-11-12 Application Number: 13167088.7 Filing Date: 2013-05-08 Inventor: Löffler, Bernhard   Schrems, Martin   Assignee: AMS AG   IPC: H01L21/311 Abstract: A device layer of a recessed semiconductor device is structured by a method comprising the steps of providing a semiconductor substrate (1) with a device layer (2) having a surface (10), forming a recess (3) extending from the surface into the substrate, and structuring the device layer. A dry film (4) is applied on the surface of the device layer after forming the recess and before structuring the device layer, so that the dry film covers the recess. A resist layer (6) is applied on or above the dry film and is patterned into a resist mask. A dry film pattern is formed from the dry film according to the pattern of the resist mask. The device layer is structured using the dry film pattern as an etch mask.
15
DE102011013228B4
Method for manufacturing semiconductor component that is three-dimensionally integrated in semiconductor chip stack
Publication/Patent Number: DE102011013228B4 Publication Date: 2014-05-28 Application Number: 102011013228 Filing Date: 2011-03-07 Inventor: Schrank, Franz   LÖffler, Bernhard   StÜckler, Ewald   Assignee: Austriamicrosystems AG   IPC: H01L21/283 Abstract: The method involves attaching a lower stop layer (13) to a conductor region (23) that is formed on a major side (2) of a semiconductor substrate (1). A handling wafer i.e. silicon substrate
16
DE102011010362B4
Semiconductor device has planar conductor that is formed on insulation layer in opposite side of substrate
Publication/Patent Number: DE102011010362B4 Publication Date: 2014-07-10 Application Number: 102011010362 Filing Date: 2011-02-04 Inventor: Kraft, Jochen Dr   Jessenig, Stefan   Schindler, Stefan   LÖffler, Bernhard   Assignee: Austriamicrosystems AG   IPC: H01L21/28 Abstract: The device has a semiconductor substrate (1) that is provided with an insulation layer (13)
17
WO2014166842A1
METHOD OF PRODUCING A THROUGH-SUBSTRATE VIA IN A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE COMPRISING A THROUGH-SUBSTRATE VIA
Publication/Patent Number: WO2014166842A1 Publication Date: 2014-10-16 Application Number: 2014056836 Filing Date: 2014-04-04 Inventor: Kraft, Jochen   Rohracher, Karl   LÖffler, Bernhard   Koppitsch, GÜnther   Assignee: AMS AG   IPC: H01L21/768 Abstract: The method comprises the steps of arranging an intermetal dielectric (2) on or above a main surface (10) of a semiconductor body (1) and at least one metal layer (5
18
EP2790211A1
Method of producing a through-substrate via in a semiconductor device and semiconductor device comprising a through-substrate via
Publication/Patent Number: EP2790211A1 Publication Date: 2014-10-15 Application Number: 13163167.3 Filing Date: 2013-04-10 Inventor: Kraft, Jochen   Löffler, Bernhard   Koppitsch, Günther   Rohracher, Karl   Assignee: AMS AG   IPC: H01L21/768 Abstract: The method comprises the steps of arranging an intermetal dielectric (2) on or above a main surface (10) of a semiconductor body (1) and at least one metal layer (5, 5') in the intermetal dielectric, and forming a via opening (3) from a rear surface (11) towards the metal layer. A stop layer (4) of electrically conductive material is arranged at the metal layer between the metal layer and the semiconductor body, and the via opening is formed at least up to the stop layer but not into the metal layer. The semiconductor device has a stop layer (4) between a section (5) of the metal layer and a metallization (19) of a through-substrate via that is arranged in the via opening, and an electrically conductive liner (6, 6') between the metal layer and the semiconductor body.
19
EP2648214A1
Semiconductor device with interconnection via in the substrate and method of production
Publication/Patent Number: EP2648214A1 Publication Date: 2013-10-09 Application Number: 12163391.1 Filing Date: 2012-04-05 Inventor: Löffler, Bernhard   Rohracher, Karl   Schrank, Franz   Siegert, Jörg   Kraft, Jochen   Assignee: austriamicrosystems AG   IPC: H01L21/768 Abstract: The semiconductor device comprises a substrate (1) of semiconductor material with a main surface (11) and an opposite surface (12), an integrated circuit component (2) in the substrate at or near the main surface, a structured metal plane (3) at a distance from the substrate above the main surface, a dielectric layer (4) between the metal plane and the substrate, an electrical interconnect (5) between the metal plane and the integrated circuit component, the interconnect traversing the dielectric layer, and an interconnection via (6) comprising a metallization (7) leading through the substrate between the main surface and the opposite surface. The metallization is connected to the metal plane via a further electrical interconnect (8) traversing the dielectric layer.
20
DE102011013228A1
Method for manufacturing semiconductor component that is three-dimensionally integrated in semiconductor chip stack
Publication/Patent Number: DE102011013228A1 Publication Date: 2012-09-13 Application Number: 102011013228 Filing Date: 2011-03-07 Inventor: Schrank, Franz   LÖffler, Bernhard   StÜckler, Ewald   Assignee: Austriamicrosystems AG   IPC: H01L21/283 Abstract: The method involves attaching a lower stop layer (13) to a conductor region (23) that is formed on a major side (2) of a semiconductor substrate (1). A handling wafer i.e. silicon substrate
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