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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US9659886B2
Method of fabricating semiconductor device having voids between top metal layers of metal interconnects
Publication/Patent Number: US9659886B2 Publication Date: 2017-05-23 Application Number: 15/193,117 Filing Date: 2016-06-27 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay chao wen   Wu, Hung-mo   Chuang, Ying-cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/528 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
2
TWI532136B
Semiconductor device and method of fabricating the same
Publication/Patent Number: TWI532136B Publication Date: 2016-05-01 Application Number: 102142675 Filing Date: 2013-11-22 Inventor: Wu, Hung Mo   Chuang, Ying Cheng   Wu, Ping Heng   Lay, Chao Wen   Lin, Chung Hsin   Assignee: Nanya Technology Corporation   IPC: H01L21/60 Abstract: The invention provides a semiconductor device including a substrate
3
US9418949B2
Semiconductor device having voids between top metal layers of metal interconnects
Publication/Patent Number: US9418949B2 Publication Date: 2016-08-16 Application Number: 14/028,554 Filing Date: 2013-09-17 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay chao wen   Wu, Hung-mo   Chuang, Ying-cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/528 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
4
US2016307859A1
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2016307859A1 Publication Date: 2016-10-20 Application Number: 15/193,117 Filing Date: 2016-06-27 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay chao wen   Wu, Hung-mo   Chuang, Ying-cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
5
TWI553832B
Capacitor array
Publication/Patent Number: TWI553832B Publication Date: 2016-10-11 Application Number: 101142555 Filing Date: 2012-11-15 Inventor: Chen, Cheng Shun   Huang, Jen Jui   Hsu, Shao Ta   Hsieh, Chun I   Tsai, Shih Shu   Lay, Chao Wen   Lin, Ching Kai   Lee, Che Chi   Assignee: Nanya Technology Corporation   IPC: H01L21/8242 Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.
6
TW201513284A
Semiconductor device and method of fabricating the same
Publication/Patent Number: TW201513284A Publication Date: 2015-04-01 Application Number: 102142675 Filing Date: 2013-11-22 Inventor: Wu, Hung Mo   Chuang, Ying Cheng   Wu, Ping Heng   Lay, Chao Wen   Lin, Chung Hsin   Assignee: Nanya Technology Corporation   IPC: H01L21/60 Abstract: The invention provides a semiconductor device including a substrate
7
US2015076698A1
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2015076698A1 Publication Date: 2015-03-19 Application Number: 14/028,554 Filing Date: 2013-09-17 Inventor: Lin, Chung-hsin   Wu, Ping-heng   Lay chao wen   Wu, Hung-mo   Chuang, Ying-cheng   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/00 Abstract: The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad.
8
US8921977B2
Capacitor array and method of fabricating the same
Publication/Patent Number: US8921977B2 Publication Date: 2014-12-30 Application Number: 13/333,564 Filing Date: 2011-12-21 Inventor: Huang, Jen Jui   Lee, Che Chi   Tsai, Shih Shu   Chen, Cheng Shun   Hsu, Shao Ta   Lay, Chao Wen   Hsieh, Chun I   Lin, Ching Kai   Assignee: Nan Ya Technology Corporation   IPC: H01L29/92 Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.
9
US8658051B2
Lithography resolution improving method
Publication/Patent Number: US8658051B2 Publication Date: 2014-02-25 Application Number: 12/119,275 Filing Date: 2008-05-12 Inventor: Cho, Kuo-yao   Wu, Wen-bin   Wang, Ya-chih   Shih, Chiang-lin   Lay chao wen   Wu, Chih-huang   Assignee: Nanya Technology Corp.   IPC: C23F1/00 Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.
10
TWI419256B
Method of flattening a recess in a substrate and fabricating a semiconductor structure
Publication/Patent Number: TWI419256B Publication Date: 2013-12-11 Application Number: 100107505 Filing Date: 2011-03-07 Inventor: Lay, Chao Wen   Lin, Ching-kai   Assignee: Nanya Technology Corp.   IPC: H01L21/76 Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore
11
US2013161786A1
CAPACITOR ARRAY AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2013161786A1 Publication Date: 2013-06-27 Application Number: 13/333,564 Filing Date: 2011-12-21 Inventor: Huang, Jen Jui   Lee, Che Chi   Tsai, Shih Shu   Chen, Cheng Shun   Hsu, Shao Ta   Lay, Chao Wen   Hsieh, Chun I.   Lin, Ching Kai   Assignee: Nan Ya Technology Corporation   IPC: H01L29/92 Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.
12
TW201327785A
Capacitor array
Publication/Patent Number: TW201327785A Publication Date: 2013-07-01 Application Number: 101142555 Filing Date: 2012-11-15 Inventor: Chen, Cheng Shun   Huang, Jen Jui   Hsu, Shao Ta   Hsieh, Chun I   Tsai, Shih Shu   Lay, Chao Wen   Lin, Ching Kai   Lee, Che Chi   Assignee: Nanya Technology Corporation   IPC: H01L21/8242 Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.
13
TW201237998A
Method of flattening a recess in a substrate and fabricating a semiconductor structure
Publication/Patent Number: TW201237998A Publication Date: 2012-09-16 Application Number: 100107505 Filing Date: 2011-03-07 Inventor: Lay, Chao Wen   Lin, Ching-kai   Assignee: Nanya Technology Corp.   IPC: H01L21/76 Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore
14
US2012034791A1
METHOD OF FLATTENING A RECESS IN A SUBSTRATE AND FABRICATING A SEMICONDUCTOR STRUCTURE
Publication/Patent Number: US2012034791A1 Publication Date: 2012-02-09 Application Number: 12/851,561 Filing Date: 2010-08-06 Inventor: Lay chao wen   Lin, Ching-kai   Assignee: Lay chao wen   Lin, Ching-Kai   IPC: H01L21/316 Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.
15
US8222163B2
Method of flattening a recess in a substrate and fabricating a semiconductor structure
Publication/Patent Number: US8222163B2 Publication Date: 2012-07-17 Application Number: 12/851,561 Filing Date: 2010-08-06 Inventor: Lay chao wen   Lin, Ching-kai   Assignee: Nanya Technology Corp.   IPC: H01L21/31 Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.
16
TWI362692B
Method for promoting a semiconductor lithography resolution
Publication/Patent Number: TWI362692B Publication Date: 2012-04-21 Application Number: 97108588 Filing Date: 2008-03-11 Inventor: Wu, Chih Huang   Wu, Wen Bin   Cho, Kuo Yao   Shih, Chiang Lin   Wang, Ya Chih   Lay, Chao Wen   Assignee: Nanya Technology Corp.   IPC: H01L21/027 Abstract: A method is provided for increasing the resolution of a pattern
17
DE102005025951B4
Verfahren zum Herstellen einer Mehrschicht-Gatestapelstruktur mit einer Metallschicht und Gatestapelstruktur für eine FET-Vorrichtung
Title (English): The claimant also alleges that, moreover, in China and No. 4,
Publication/Patent Number: DE102005025951B4 Publication Date: 2010-05-12 Application Number: 102005025951 Filing Date: 2005-06-06 Inventor: Schmidt, Michael   Goldbach, Matthias   Schupke, Kristin   Jakubowski, Frank   Koepe, Ralf   Lay chao wen   Huang, Cheng Chih   Assignee: Nanya Technology Corporation   Qimonda AG   IPC: H01L21/28 Abstract: Verfahren zum Herstellen einer Mehrschicht-Gatestapelstruktur mit einer Metallschicht und einer Gatestapelstruktur für ein FET-Bauelement. DOLLAR A Eine Mehrschicht-Gatestapelstruktur (3) eines Feldeffekttransistor-Bauelements wird hergestellt durch Aufbringen eines Gateelektrodenschichtstapels mit einer Polysiliziumschicht (31')
18
TW200917417A
Interconnection process
Publication/Patent Number: TW200917417A Publication Date: 2009-04-16 Application Number: 96136780 Filing Date: 2007-10-01 Inventor: Huang, Jen-jui   Lay chao wen   Assignee: Nanya Technology Corporation   IPC: H01L21/768 Abstract: An interconnection process is provided. A substrate is provided. A plurality of gate structure is disposed on the substrate
19
US2009087978A1
INTERCONNECT MANUFACTURING PROCESS
Publication/Patent Number: US2009087978A1 Publication Date: 2009-04-02 Application Number: 11/958,974 Filing Date: 2007-12-18 Inventor: Lay chao wen   Huang, Jen-jui   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/4763 Abstract: An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the substrate. A contact opening is formed in the dielectric layer between two neighboring gate structures to expose the liner on the doped region and on a portion of the top surface and a portion of the sidewall of each of the gate structures. A polymer material is deposited on the liner on the portion of the top surface of each of the gate structures and on the doped region. The liner on the doped regions is removed. A conductive layer is filled in the contact opening, which is free of electrical connection to the gate structures.
20
TW200939299A
Method for promoting a semiconductor lithography resolution
Publication/Patent Number: TW200939299A Publication Date: 2009-09-16 Application Number: 97108588 Filing Date: 2008-03-11 Inventor: Wu, Chih Huang   Wu, Wen Bin   Cho, Kuo Yao   Shih, Chiang Lin   Wang, Ya Chih   Lay, Chao Wen   Assignee: Nanya Technology Corp.   IPC: H01L21/027 Abstract: A method is provided for increasing the resolution of a pattern
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