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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US2020243510A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020243510A1 Publication Date: 2020-07-30 Application Number: 16/848,925 Filing Date: 2020-04-15 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Chao, Yi-ping   Lee chih lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
2 US10636782B2
Systems and methods for protecting a semiconductor device
Publication/Patent Number: US10636782B2 Publication Date: 2020-04-28 Application Number: 16/192,883 Filing Date: 2018-11-16 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Chao, Yi-ping   Lee chih lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
3 US2020174105A1
METHOD AND APPARATUS FOR A HYBRID TIME-OF-FLIGHT SENSOR WITH HIGH DYNAMIC RANGE
Publication/Patent Number: US2020174105A1 Publication Date: 2020-06-04 Application Number: 16/656,424 Filing Date: 2019-10-17 Inventor: Yin, Chin   Wu, Meng-hsiu   Lee chih lin   Chao, Calvin Yi-ping   Yeh, Shang-fu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: G01S7/486 Abstract: Disclosed is a time-of-flight sensing apparatus and method. In one embodiment, a system for time-of-flight (TOF) sensing, comprising: a detector array comprising a plurality of single-photon avalanche detectors (SPADs); and a control circuit comprising at least two digital control arrays coupled to the detector array, a counter array coupled to the at least two digital control arrays, and a logical control unit coupled to the counter array and the at least two digital control arrays, wherein the detector array is configured to receive at least one reflected light pulse from a target, wherein a first digital control array, the counter array, and the logical control unit of the control circuit are configured to receive at least one avalanche pulses from each of the plurality of SPADs to determine a first distance between the detector array and the target in a first TOF mode, and wherein a second digital control array, the counter array, and the logical control unit of the control circuit are configured to receive the at least one avalanche pulse from the each of the plurality of SPADs to determine a second distance between the detector array and the target in a second TOF mode.
4 US202018642A1
Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing
Publication/Patent Number: US202018642A1 Publication Date: 2020-01-16 Application Number: 20/191,645 Filing Date: 2019-06-27 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Lee chih lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H03L7/081 Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.
5 US10638078B2
Counter, counting method and apparatus for image sensing
Publication/Patent Number: US10638078B2 Publication Date: 2020-04-28 Application Number: 15/995,143 Filing Date: 2018-06-01 Inventor: Yeh, Shang-fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Lee chih lin   Yin, Chin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/374 Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.
6 US2020018642A1
Time-To-Digital Converter Circuit and Method for Single-Photon Avalanche Diode Based Depth Sensing
Publication/Patent Number: US2020018642A1 Publication Date: 2020-01-16 Application Number: 16/454,358 Filing Date: 2019-06-27 Inventor: Yin, Chin   Lee chih lin   Yeh, Shang-fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: G01J1/44 Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.
7 US2020119144A1
SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE
Publication/Patent Number: US2020119144A1 Publication Date: 2020-04-16 Application Number: 16/716,299 Filing Date: 2019-12-16 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh, Shang-fu   Lee chih lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
8 US201988640A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US201988640A1 Publication Date: 2019-03-21 Application Number: 20/181,619 Filing Date: 2018-11-16 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Lee chih lin   Chao, Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
9 US2019088640A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2019088640A1 Publication Date: 2019-03-21 Application Number: 16/192,883 Filing Date: 2018-11-16 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Chao, Yi-ping   Lee chih lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
10 US10270992B1
Sampling device and method for reducing noise
Publication/Patent Number: US10270992B1 Publication Date: 2019-04-23 Application Number: 15/828,292 Filing Date: 2017-11-30 Inventor: Yeh, Shang-fu   Lee chih lin   Yin, Chin   Chou, Kuo-yu   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H04N5/357 Abstract: A device includes a current source and sampling units. Each of the sampling units includes a transistor and a capacitor electrically coupled to a gate of the transistor. The sampling units are sequentially activated such that the capacitor samples a voltage of a column line of a pixel array and are activated together such that the transistor is turned on according to the sampled voltage of the capacitor, to drain a current from the current source through an output node to generate an output voltage thereat.
11 US2019373200A1
COUNTER, COUNTING METHOD AND APPARATUS FOR IMAGE SENSING
Publication/Patent Number: US2019373200A1 Publication Date: 2019-12-05 Application Number: 15/995,143 Filing Date: 2018-06-01 Inventor: Yeh, Shang-fu   Chou, Kuo-yu   Chao, Calvin Yi-ping   Lee chih lin   Yin, Chin   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/376 Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.
12 US10277849B2
System and method for high-speed down-sampled CMOS image sensor readout
Publication/Patent Number: US10277849B2 Publication Date: 2019-04-30 Application Number: 15/941,431 Filing Date: 2018-03-30 Inventor: Chao, Calvin Yi-ping   Chang, Chin-hao   Chou, Kuo-yu   Yeh, Shang-fu   Lee chih lin   Huang, Chiao-yi   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/345 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
13 US10510835B2
Semiconductor device with low random telegraph signal noise
Publication/Patent Number: US10510835B2 Publication Date: 2019-12-17 Application Number: 15/965,610 Filing Date: 2018-04-27 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh, Shang-fu   Lee chih lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
14 US2019333989A1
SEMICONDUCTOR DEVICE WITH LOW RANDOM TELEGRAPH SIGNAL NOISE
Publication/Patent Number: US2019333989A1 Publication Date: 2019-10-31 Application Number: 15/965,610 Filing Date: 2018-04-27 Inventor: Chou, Kuo-yu   Takahashi, Seiji   Yeh, Shang-fu   Lee chih lin   Yin, Chin   Chao, Calvin Yi-ping   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L29/06 Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.
15 US2018040606A1
SYSTEMS AND METHODS FOR PROTECTING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2018040606A1 Publication Date: 2018-02-08 Application Number: 15/226,995 Filing Date: 2016-08-03 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Chao, Yi-ping   Lee chih lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
16 TW201816978A
Systems and methods for protecting a semiconductor device
Publication/Patent Number: TW201816978A Publication Date: 2018-05-01 Application Number: 106113722 Filing Date: 2017-04-25 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Lee chih lin   Chao, Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Company Ltd.   IPC: H01L23/60 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
17 US10157906B2
Systems and methods for protecting a semiconductor device
Publication/Patent Number: US10157906B2 Publication Date: 2018-12-18 Application Number: 15/226,995 Filing Date: 2016-08-03 Inventor: Chou, Kuo-yu   Yeh, Shang-fu   Chao, Yi-ping   Lee chih lin   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L27/02 Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
18 US2018227531A1
SYSTEM AND METHOD FOR HIGH-SPEED DOWN-SAMPLED CMOS IMAGE SENSOR READOUT
Publication/Patent Number: US2018227531A1 Publication Date: 2018-08-09 Application Number: 15/941,431 Filing Date: 2018-03-30 Inventor: Huang, Chiao-yi   Lee chih lin   Yeh, Shang-fu   Chou, Kuo-yu   Chang, Chin-hao   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/378 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
19 TW201801521A
System and method for high-speed down sampled CMOS image sensor readout
Publication/Patent Number: TW201801521A Publication Date: 2018-01-01 Application Number: 105135352 Filing Date: 2016-11-01 Inventor: Chou, Kuo-yu   Chang, Chin-hao   Yeh, Shang-fu   Huang, Chiao-yi   Chao, Calvin Yi-ping   Lee chih lin   Assignee: Taiwan Semiconductor Manufacturing Company Ltd.   IPC: H04N5/3745 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.
20 US9955096B2
System and method for high-speed down-sampled CMOS image sensor readout
Publication/Patent Number: US9955096B2 Publication Date: 2018-04-24 Application Number: 15/076,983 Filing Date: 2016-03-22 Inventor: Huang, Chiao-yi   Chou, Kuo-yu   Lee chih lin   Chang, Chin-hao   Yeh, Shang-fu   Chao, Calvin Yi-ping   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H04N5/378 Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.