Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
US9887293B2
Semiconductor device
Publication/Patent Number: US9887293B2 Publication Date: 2018-02-06 Application Number: 15/191,542 Filing Date: 2016-06-24 Inventor: Ku, Chi-fa   Lee chung yuan   Wang, Sanpo   Lin, Chen-bin   Chen, Ding-lung   Zhou, Zhibiao   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L29/788 Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.
2
US9935099B2
Semiconductor device
Publication/Patent Number: US9935099B2 Publication Date: 2018-04-03 Application Number: 14/956,398 Filing Date: 2015-12-02 Inventor: Zhou, Zhibiao   Lin, Chen-bin   Xing, Su   Shuai, Chi-chang   Lee chung yuan   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L27/06 Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.
3
US2018138316A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2018138316A1 Publication Date: 2018-05-17 Application Number: 15/853,875 Filing Date: 2017-12-25 Inventor: Ku, Chi-fa   Lee chung yuan   Wang, Sanpo   Lin, Chen-bin   Chen, Ding-lung   Zhou, Zhibiao   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L29/788 Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.
4
US10056493B2
Semiconductor device
Publication/Patent Number: US10056493B2 Publication Date: 2018-08-21 Application Number: 15/853,875 Filing Date: 2017-12-25 Inventor: Ku, Chi-fa   Lee chung yuan   Wang, Sanpo   Lin, Chen-bin   Chen, Ding-lung   Zhou, Zhibiao   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L29/792 Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.
5
US2017338351A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2017338351A1 Publication Date: 2017-11-23 Application Number: 15/191,542 Filing Date: 2016-06-24 Inventor: Zhou, Zhibiao   Chen, Ding-lung   Lin, Chen-bin   Wang, Sanpo   Lee chung yuan   Ku, Chi-fa   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L29/786 Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide-semiconductor layer is disposed on the first gate electrode on the substrate. The source/drain regions are disposed on the oxide-semiconductor layer. The first dielectric layer covers on the oxide-semiconductor layer and source/drain regions. A second gate electrode is disposed between source/drain regions and partially covers the oxide-semiconductor layer. The oxide-semiconductor layer may be optionally disposed between the first gate electrode and the oxide-semiconductor layer or be disposed on the second gate electrode.
6
TW201715699A
Semiconductor device
Publication/Patent Number: TW201715699A Publication Date: 2017-05-01 Application Number: 104135712 Filing Date: 2015-10-30 Inventor: Lee chung yuan   Shuai, Chi-chang   Lin, Chen-bin   Zhou, Zhibiao   Xing, Su   Assignee: United Microelectronics Corp.   IPC: H01L27/06 Abstract: The present invention provides a semiconductor device including a semiconductor substrate
7
US2017125402A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2017125402A1 Publication Date: 2017-05-04 Application Number: 14/956,398 Filing Date: 2015-12-02 Inventor: Zhou, Zhibiao   Lin, Chen-bin   Xing, Su   Shuai, Chi-chang   Lee chung yuan   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L27/06 Abstract: The present invention provides a semiconductor device including a semiconductor substrate, a first well, a second well, a gate electrode, an oxide semiconductor structure and a diode. The first well is disposed in the semiconductor substrate and has a first conductive type, and the second well is also disposed in the semiconductor substrate, adjacent to the first well, and has a second conductive type. The gate electrode is disposed on the first well. The oxide semiconductor structure is disposed on the semiconductor substrate and electrically connected to the second well. The diode is disposed between the first well and the second well.
8
TW201742234A
Semiconductor device
Publication/Patent Number: TW201742234A Publication Date: 2017-12-01 Application Number: 105115666 Filing Date: 2016-05-20 Inventor: Lee chung yuan   Lin, Chen-bin   Ku, Chi-fa   Zhou, Zhibiao   Chen, Ding Lung   Wang, San Po   Assignee: United Microelectronics Corp.   IPC: H01L27/115 Abstract: Present invention provides a semiconductor device, including a substrate, an oxide semiconductor layer, two source/drain regions, a dielectric layer, a first gate electrode, a second gate electrode and a charge storage structure. The oxide semiconductor layer is disposed on the first gate electrode on the substrate. The two source/drain regions are disposed on the oxide semiconductor layer. The dielectric layer covers the oxide semiconductor layer and the two source/drain regions. The second gate electrode is disposed between the two source/drain regions and partially overlaps the oxide semiconductor layer. The charge storing structure is optionally disposed between the first gate and the oxide semiconductor layer.
9
TWI520351B
Stack capcaitor and manufacturing method thereof
Publication/Patent Number: TWI520351B Publication Date: 2016-02-01 Application Number: 102108514 Filing Date: 2013-03-11 Inventor: Lee, Chung Yuan   Chiang, Hsu   Lee, Tzung Han   Hu, Yaw Wen   Wu, Sheng Hsiung   Assignee: INOTERA MEMORIES, INC.   IPC: H01L21/8239 Abstract: The present disclosure provides a stack capacitor and the manufacturing method thereof
10
TWI520286B
Semiconductor device with tsv
Publication/Patent Number: TWI520286B Publication Date: 2016-02-01 Application Number: 102133181 Filing Date: 2013-09-13 Inventor: Lee, Chung Yuan   Hu, Yaw-wen   Chiang, Hsu   Lee, Tzung Han   Assignee: INOTERA MEMORIES, INC.   IPC: H01L21/768 Abstract: The semiconductor device with TSV of the instant disclosure includes a substrate
11
US9455202B2
Mask set and method for fabricating semiconductor device by using the same
Publication/Patent Number: US9455202B2 Publication Date: 2016-09-27 Application Number: 14/289,657 Filing Date: 2014-05-29 Inventor: Lee, Wei-chi   Wang, Yu-lin   Lee chung yuan   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L21/8238 Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.
12
TWI531025B
Memory cell unit
Publication/Patent Number: TWI531025B Publication Date: 2016-04-21 Application Number: 102110965 Filing Date: 2013-03-27 Inventor: Lee, Chung Yuan   Hu, Yaw-wen   Chiang, Hsu   Lee, Tzung Han   Liao, Hung Chang   Wu, Sheng Hsiung   Assignee: INOTERA MEMORIES, INC.   IPC: H01L21/762 Abstract: A memory cell unit includes a substrate
13
TWI488288B
Semiconductor layout structure
Publication/Patent Number: TWI488288B Publication Date: 2015-06-11 Application Number: 101141313 Filing Date: 2012-11-07 Inventor: Lee, Chung Yuan   Lee, Tzung Han   Assignee: INOTERA MEMORIES, INC.   IPC: G06F17/50 Abstract: A semiconductor layout structure includes multiple active blocks which are disposed on a substrate
14
US9000532B2
Vertical PMOS field effect transistor and manufacturing method thereof
Publication/Patent Number: US9000532B2 Publication Date: 2015-04-07 Application Number: 14/316,972 Filing Date: 2014-06-27 Inventor: Chen, Hsin-huei   Lee chung yuan   Assignee: Inotera Memories, Inc.   IPC: H01L29/76 Abstract: A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.
15
TW201511202A
Semiconductor device with tsv
Publication/Patent Number: TW201511202A Publication Date: 2015-03-16 Application Number: 102133181 Filing Date: 2013-09-13 Inventor: Lee, Chung Yuan   Hu, Yaw-wen   Chiang, Hsu   Lee, Tzung Han   Assignee: INOTERA MEMORIES, INC.   IPC: H01L21/768 Abstract: The semiconductor device with TSV of the instant disclosure includes a substrate
16
US2015348850A1
MASK SET AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE BY USING THE SAME
Publication/Patent Number: US2015348850A1 Publication Date: 2015-12-03 Application Number: 14/289,657 Filing Date: 2014-05-29 Inventor: Lee, Wei-chi   Wang, Yu-lin   Lee chung yuan   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L21/8238 Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.
17
TWI497574B
Semiconductor structure
Publication/Patent Number: TWI497574B Publication Date: 2015-08-21 Application Number: 101140493 Filing Date: 2012-11-01 Inventor: Lee, Chung Yuan   Hu, Yaw-wen   Chiang, Hsu   Lee, Tzung Han   Liao, Hung Chang   Wu, Sheng Hsiung   Assignee: INOTERA MEMORIES, INC.   IPC: H01L21/28 Abstract: A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source
18
TWI506766B
Semiconductor device and manufacturing method therefor
Publication/Patent Number: TWI506766B Publication Date: 2015-11-01 Application Number: 102110966 Filing Date: 2013-03-27 Inventor: Lee, Chung Yuan   Hu, Yaw-wen   Chiang, Hsu   Lee, Tzung Han   Liao, Hung Chang   Wu, Sheng Hsiung   Assignee: INOTERA MEMORIES, INC.   IPC: H01L27/108 Abstract: A semiconductor device includes an active area array disposed in a substrate
19
US2015076666A1
SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON VIA
Publication/Patent Number: US2015076666A1 Publication Date: 2015-03-19 Application Number: 14/107,214 Filing Date: 2013-12-16 Inventor: Chiang, Hsu   Hu, Yaw-wen   Lee, Tzung-han   Lee chung yuan   Assignee: INOTERA MEMORIES, INC.   IPC: H01L23/48 Abstract: A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface.
20
US2015123130A1
TEST KEY STRUCTURE
Publication/Patent Number: US2015123130A1 Publication Date: 2015-05-07 Application Number: 14/072,905 Filing Date: 2013-11-06 Inventor: Liao, Mei-chih   Tao, Yi-fang   Wang, Yu-lin   Lee chung yuan   Assignee: UNITED MICROELECTRONICS CORP.   IPC: H01L21/66 Abstract: A test key structure is provided. The test key structure comprises at least one semiconductor element. Each of the at least one semiconductor element including a well, a source region, a drain region and a gate. The source region is disposed in the well. The drain region is disposed in the well and separated from the source region. The gate is disposed above the well. The source region, the drain region and the well have the same type of doping.
Total 10 pages