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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1 US10741482B2
Semiconductor device package
Publication/Patent Number: US10741482B2 Publication Date: 2020-08-11 Application Number: 15/858,939 Filing Date: 2017-12-29 Inventor: Lee yu ying   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/498 Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.
2 US2020350239A1
SEMICONDUCTOR DEVICE PACKAGE
Publication/Patent Number: US2020350239A1 Publication Date: 2020-11-05 Application Number: 16/932,690 Filing Date: 2020-07-17 Inventor: Lee yu ying   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/498 Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.
3 US2020259058A1
SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2020259058A1 Publication Date: 2020-08-13 Application Number: 16/862,447 Filing Date: 2020-04-29 Inventor: Wu, Mei-yi   Lai, Lu-ming   Lee yu ying   Chang, Yung-yi   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L33/62 Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.
4 US10665765B2
Semiconductor device package and a method of manufacturing the same
Publication/Patent Number: US10665765B2 Publication Date: 2020-05-26 Application Number: 15/860,567 Filing Date: 2018-01-02 Inventor: Wu, Mei-yi   Lai, Lu-ming   Lee yu ying   Chang, Yung-yi   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L33/62 Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.
5 US10734337B2
Semiconductor package device having glass transition temperature greater than binding layer temperature
Publication/Patent Number: US10734337B2 Publication Date: 2020-08-04 Application Number: 16/293,606 Filing Date: 2019-03-05 Inventor: Chen, Kuang-hsiung   Tsai, Yu-hsuan   Lee yu ying   Wang, Sheng-ming   Syu, Wun-jheng   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/28 Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
6 US10483196B2
Embedded trace substrate structure and semiconductor package structure including the same
Publication/Patent Number: US10483196B2 Publication Date: 2019-11-19 Application Number: 15/887,780 Filing Date: 2018-02-02 Inventor: Lee yu ying   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/00 Abstract: A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.
7 US2019206775A1
SEMICONDUCTOR DEVICE PACKAGE
Publication/Patent Number: US2019206775A1 Publication Date: 2019-07-04 Application Number: 15/858,939 Filing Date: 2017-12-29 Inventor: Lee yu ying   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/498 Abstract: A semiconductor device package includes a carrier, a first conductive post and a first adhesive layer. The first conductive post is disposed on the carrier. The first conductive post includes a lower surface facing the carrier, an upper surface opposite to the lower surface and a lateral surface extended between the upper surface and the lower surface. The first adhesive layer surrounds a portion of the lateral surface of the first conductive post. The first adhesive layer comprises conductive particles and an adhesive. The first conductive post has a height measured from the upper surface to the lower surface and a width. The height is greater than the width.
8 US10446411B2
Semiconductor device package with a conductive post
Publication/Patent Number: US10446411B2 Publication Date: 2019-10-15 Application Number: 16/102,527 Filing Date: 2018-08-13 Inventor: Chen, Tien-szu   Chen, Kuang-hsiung   Wang, Sheng-ming   Lee yu ying   Peng, Yu-tzu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/48 Abstract: A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.
9 US10224298B2
Semiconductor package device having glass transition temperature greater than binding layer temperature
Publication/Patent Number: US10224298B2 Publication Date: 2019-03-05 Application Number: 15/649,474 Filing Date: 2017-07-13 Inventor: Chen, Kuang-hsiung   Tsai, Yu-hsuan   Lee yu ying   Wang, Sheng-ming   Syu, Wun-jheng   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/28 Abstract: In one or more embodiments, a micro-electromechanical systems (MEMS) package structure comprises a MEMS die, a conductive pillar adjacent to the MEMS die, a package body and a binding layer on the package body. The package body encapsulates the MEMS die and the conductive pillar, and exposes a top surface of the conductive pillar. A glass transition temperature (Tg) of the package body is greater than a temperature for forming the binding layer (Tc).
10 US2019198469A1
SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2019198469A1 Publication Date: 2019-06-27 Application Number: 16/293,606 Filing Date: 2019-03-05 Inventor: Chen, Kuang-hsiung   Tsai, Yu-hsuan   Lee yu ying   Wang, Sheng-ming   Syu, Wun-jheng   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L23/00 Abstract: A micro-electromechanical systems (MEMS) package structure includes: (1) a circuit layer; (2) a MEMS die with an active surface, wherein the active surface faces the circuit layer; (3) a conductive pillar adjacent to the MEMS die; and (4) a package body encapsulating the MEMS die and the conductive pillar, and exposing a top surface of the conductive pillar.
11 US10515884B2
Substrate having a conductive structure within photo-sensitive resin
Publication/Patent Number: US10515884B2 Publication Date: 2019-12-24 Application Number: 14/624,388 Filing Date: 2015-02-17 Inventor: Chen, Tien-szu   Chen, Kuang-hsiung   Wang, Sheng-ming   Lee yu ying   Tsai, Li-chuan   Lee, Chih-cheng   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/498 Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.
12 US2018240745A1
SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
Publication/Patent Number: US2018240745A1 Publication Date: 2018-08-23 Application Number: 15/887,780 Filing Date: 2018-02-02 Inventor: Lee yu ying   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L21/683 Abstract: A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.
13 US9911702B2
Semiconductor package structure and fabrication method thereof
Publication/Patent Number: US9911702B2 Publication Date: 2018-03-06 Application Number: 14/268,981 Filing Date: 2014-05-02 Inventor: Lee yu ying   Chen, Kuang-hsiung   Wang, Sheng-ming   Chen, Tien-szu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/498 Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.
14 US2018145037A1
SEMICONDUCTOR PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
Publication/Patent Number: US2018145037A1 Publication Date: 2018-05-24 Application Number: 15/873,784 Filing Date: 2018-01-17 Inventor: Lee yu ying   Chen, Kuang-hsiung   Wang, Sheng-ming   Chen, Tien-szu   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L21/56 Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.
15 US2018233643A1
SEMICONDUCTOR DEVICE PACKAGE AND A METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2018233643A1 Publication Date: 2018-08-16 Application Number: 15/860,567 Filing Date: 2018-01-02 Inventor: Chang, Yung-yi   Lee yu ying   Lai, Lu-ming   Wu, Mei-yi   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L33/60 Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.
16 US10002843B2
Semiconductor substrate structure, semiconductor package and method of manufacturing the same
Publication/Patent Number: US10002843B2 Publication Date: 2018-06-19 Application Number: 14/667,317 Filing Date: 2015-03-24 Inventor: Lee yu ying   Wang, Sheng-ming   Chen, Kuang-hsiung   Chen, Tien-szu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H05K3/10 Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.
17 US9984989B2
Semiconductor substrate and semiconductor package structure
Publication/Patent Number: US9984989B2 Publication Date: 2018-05-29 Application Number: 14/855,849 Filing Date: 2015-09-16 Inventor: Lee yu ying   Chen, Kuang-hsiung   Wang, Sheng-ming   Chen, Tien-szu   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L23/498 Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.
18 US10103110B2
Semiconductor package structure and fabrication method thereof
Publication/Patent Number: US10103110B2 Publication Date: 2018-10-16 Application Number: 15/873,784 Filing Date: 2018-01-17 Inventor: Chen, Tien-szu   Wang, Sheng-ming   Chen, Kuang-hsiung   Lee yu ying   Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.   IPC: H01L21/00 Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units which comprise a substrate unit; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures which comprise a semiconductor package structure comprising the substrate unit, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.
19 TW201841395A
Semiconductor device package and a method of manufacturing the same
Publication/Patent Number: TW201841395A Publication Date: 2018-11-16 Application Number: 107104080 Filing Date: 2018-02-06 Inventor: Wu, Mei-yi   Chang, Yung-yi   Lai, Lu-ming   Lee yu ying   Assignee: Advanced Semiconductor Engineering, Inc.   IPC: H01L33/62 Abstract: A semiconductor device package includes a carrier, a semiconductor device, a lid, a conductive post, a first patterned conductive layer, a conductive element disposed between the first conductive post and the first patterned conductive layer, and an adhesive layer disposed between the lid and the carrier. The conductive post is electrically connected to the first patterned conductive layer. The semiconductor device is electrically connected to the first patterned conductive layer. The lid is disposed on the carrier, and the lid includes a second patterned conductive layer electrically connected to the first conductive post.