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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2020219920A1
IMAGE SENSOR AND METHOD OF FABRICATING THE SAME
Publication/Patent Number: US2020219920A1 Publication Date: 2020-07-09 Application Number: 16/555,151 Filing Date: 2019-08-29 Inventor: Hur, Jaesung   Kim, Youngtak   Lim, Hajin   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L27/146 Abstract: An image sensor and a method of fabricating an image sensor, the image sensor including a plurality of color filters spaced apart from each other on a semiconductor substrate; a protective layer covering sidewalls of the color filters and top surfaces of the color filters; and a low-refractive pattern filling a space between the color filters.
2
US2020381473A1
IMAGE SENSOR AND METHOD OF FABRICATING AN IMAGE SENSOR
Publication/Patent Number: US2020381473A1 Publication Date: 2020-12-03 Application Number: 16/711,301 Filing Date: 2019-12-11 Inventor: Kim, Changhwa   Kim, Kwansik   Kim, Dongchan   Park, Sang-su   Lee, Beomsuk   Lee, Taeyon   Lim, Hajin   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L27/146 Abstract: An image sensor and a method of fabricating the image sensor, the image sensor including a semiconductor substrate having a first floating diffusion region, a molding pattern over the first floating diffusion region and including an opening, a first photoelectric conversion part at a surface of the semiconductor substrate, and a first transfer transistor connecting the first photoelectric conversion part to the first floating diffusion region. The first transfer transistor includes a channel pattern in the opening and a first transfer gate electrode. The channel pattern includes an oxide semiconductor. The channel pattern also includes a sidewall portion that covers a side surface of the opening, and a center portion that extends from the sidewall portion to a region over the first transfer gate electrode.
3
KR20190047886A
conversation survey providing system and method using artificial intelligence chatbot
Publication/Patent Number: KR20190047886A Publication Date: 2019-05-09 Application Number: 20170142241 Filing Date: 2017-10-30 Inventor: Park, Jeong Ho   Daeyoung, Kim   Lim, Hajin   Ko, Nam Gil   Assignee: KO, NAM GIL   IPC: G06Q50/30 Abstract: The present invention relates to a system for providing a conversation survey using an artificial intelligence chatbot and a method thereof and, more specifically, to a system for providing a conversation survey using an artificial intelligence chatbot and a method thereof capable of proceeding a survey while having a conversation with a chatbot through a messenger application by being interlocked with an existing messenger application installed on a user terminal through a chatbot server. In addition, the system for providing a conversation survey using an artificial intelligence chatbot comprises a communication proceeding unit, an artificial intelligence chatbot, and a chatbot server.
4
KR101980727B1
conversation survey providing system and method using artificial intelligence chatbot
Publication/Patent Number: KR101980727B1 Publication Date: 2019-05-21 Application Number: 20170142241 Filing Date: 2017-10-30 Inventor: Park, Jeong Ho   Daeyoung, Kim   Lim, Hajin   Ko, Nam Gil   Assignee: KO, NAM GIL   IPC: G06N3/02 Abstract: The present invention relates to a system for providing a conversation survey using an artificial intelligence chatbot and a method thereof and, more specifically, to a system for providing a conversation survey using an artificial intelligence chatbot and a method thereof capable of proceeding a survey while having a conversation with a chatbot through a messenger application by being interlocked with an existing messenger application installed on a user terminal through a chatbot server. In addition, the system for providing a conversation survey using an artificial intelligence chatbot comprises a communication proceeding unit, an artificial intelligence chatbot, and a chatbot server.
5
US9142461B2
Methods of fabricating semiconductor devices
Publication/Patent Number: US9142461B2 Publication Date: 2015-09-22 Application Number: 14/289,076 Filing Date: 2014-05-28 Inventor: Do, Jinho   Lim, Hajin   Kim, Weonhong   Hong, Kyungil   Song, Moonkyun   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/336 Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
6
US8735951B2
Semiconductor device having diffusion barrier element injection region
Publication/Patent Number: US8735951B2 Publication Date: 2014-05-27 Application Number: 13/327,960 Filing Date: 2011-12-16 Inventor: Lim, Hajin   Park, Moonhan   Do, Jinho   Song, Moonkyun   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor device includes an isolation pattern disposed on a substrate, the isolation pattern defining an active part, a gate pattern crossing the active part on the substrate, the gate pattern including a dielectric pattern and a first conductive pattern, and the dielectric pattern being between the active part and the first conductive pattern, a pair of doping regions in the active part adjacent to side walls of the gate pattern, the gate pattern being between the pair of doping regions, and a diffusion barrier element injection region disposed in an upper region of the active part.
7
US2014273382A1
METHODS OF FABRICATING SEMICONDUCTOR DEVICES
Publication/Patent Number: US2014273382A1 Publication Date: 2014-09-18 Application Number: 14/289,076 Filing Date: 2014-05-28 Inventor: Do, Jinho   Lim, Hajin   Kim, Weonhong   Hong, Kyungil   Song, Moonkyun   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/8234 Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
8
US8778753B2
Methods of fabricating semiconductor devices
Publication/Patent Number: US8778753B2 Publication Date: 2014-07-15 Application Number: 13/423,748 Filing Date: 2012-03-19 Inventor: Do, Jinho   Lim, Hajin   Kim, Weonhong   Hong, Kyungil   Song, Moonkyun   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/8238 Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
9
US2014175569A1
SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC LAYER
Publication/Patent Number: US2014175569A1 Publication Date: 2014-06-26 Application Number: 14/190,346 Filing Date: 2014-02-26 Inventor: Kim, Weonhong   Joo, Dae-kwon   Lim, Hajin   Do, Jinho   Hong, Kyungil   Song, Moonkyun   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L29/51 Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.
10
US8673711B2
Methods of fabricating a semiconductor device having a high-K gate dielectric layer and semiconductor devices fabricated thereby
Publication/Patent Number: US8673711B2 Publication Date: 2014-03-18 Application Number: 13/240,217 Filing Date: 2011-09-22 Inventor: Kim, Weonhong   Joo, Dae-kwon   Lim, Hajin   Do, Jinho   Hong, Kyungil   Song, Moonkyun   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/8238 Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.
11
US8912611B2
Semiconductor device having a high-K gate dielectric layer
Publication/Patent Number: US8912611B2 Publication Date: 2014-12-16 Application Number: 14/190,346 Filing Date: 2014-02-26 Inventor: Kim, Weonhong   Joo, Dae-kwon   Lim, Hajin   Do, Jinho   Hong, Kyungil   Song, Moonkyun   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/02 Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.
12
US8575705B2
Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same
Publication/Patent Number: US8575705B2 Publication Date: 2013-11-05 Application Number: 12/964,173 Filing Date: 2010-12-09 Inventor: Lim, Hajin   Kim, Myungsun   Chung, Hoi Sung   Do, Jinho   Kim, Weonhong   Song, Moonkyun   Joo, Dae-kwon   Assignee: Samsung Electronics Co., Ltd.   IPC: H01L21/70 Abstract: A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.
13
US2012161211A1
SEMICONDUCTOR DEVICE
Publication/Patent Number: US2012161211A1 Publication Date: 2012-06-28 Application Number: 13/327,960 Filing Date: 2011-12-16 Inventor: Lim, Hajin   Park, Moonhan   Do, Jinho   Song, Moonkyun   Assignee: LIM, Hajin   Park, Moonhan   Do, Jinho   Song, Moonkyun   IPC: H01L29/78 Abstract: A semiconductor device includes an isolation pattern disposed on a substrate, the isolation pattern defining an active part, a gate pattern crossing the active part on the substrate, the gate pattern including a dielectric pattern and a first conductive pattern, and the dielectric pattern being between the active part and the first conductive pattern, a pair of doping regions in the active part adjacent to side walls of the gate pattern, the gate pattern being between the pair of doping regions, and a diffusion barrier element injection region disposed in an upper region of the active part.
14
US2012244670A1
METHODS OF FABRICATING SEMICONDUCTOR DEVICES
Publication/Patent Number: US2012244670A1 Publication Date: 2012-09-27 Application Number: 13/423,748 Filing Date: 2012-03-19 Inventor: Do, Jinho   Lim, Hajin   Kim, Weonhong   Hong, Kyungil   Song, Moonkyun   Assignee: SAMSUNG ELECTRONICS CO., LTD.   IPC: H01L21/8238 Abstract: A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.
15
US2012129310A1
METHODS OF FABRICATING A SEMICONDUCTOR DEVICE HAVING A HIGH-K GATE DIELECTRIC LAYER AND SEMICONDUCTOR DEVICES FABRICATED THEREBY
Publication/Patent Number: US2012129310A1 Publication Date: 2012-05-24 Application Number: 13/240,217 Filing Date: 2011-09-22 Inventor: Kim, Weonhong   Joo, Dae-kwon   Lim, Hajin   Do, Jinho   Hong, Kyungil   Song, Moonkyun   Assignee: KIM, WeonHong   Joo, Dae-Kwon   Lim, Hajin   Do, Jinho   Hong, Kyungil   Song, Moonkyun   IPC: H01L21/336 Abstract: A method of fabricating a semiconductor device includes forming a lower interfacial layer on a semiconductor layer, the lower interfacial layer being a nitride layer, forming an intermediate interfacial layer on the lower interfacial layer, the intermediate interfacial layer being an oxide layer, and forming a high-k dielectric layer on the intermediate interfacial layer. The high-k dielectric layer has a dielectric constant that is higher than dielectric constants of the lower interfacial layer and the intermediate interfacial layer.
16
US2011175141A1
SEMICONDUCTOR DEVICES INCLUDING MOS TRANSISTORS HAVING AN OPTIMIZED CHANNEL REGION AND METHODS OF FABRICATING THE SAME
Publication/Patent Number: US2011175141A1 Publication Date: 2011-07-21 Application Number: 12/964,173 Filing Date: 2010-12-09 Inventor: Lim, Hajin   Kim, Myungsun   Chung, Hoi Sung   Do, Jinho   Kim, Weonhong   Song, Moonkyun   Joo, Dae-kwon   Assignee: LIM, Hajin   Kim, Myungsun   Chung, Hoi Sung   Do, Jinho   Kim, Weonhong   Song, Moonkyun   Joo, Dae-Kwon   IPC: H01L29/04 Abstract: A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.