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1
US2021057524A1
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2021057524A1 Publication Date: 2021-02-25 Application Number: 16/548,744 Filing Date: 2019-08-22 Inventor: Lin shih yen   Chen, Kuan-chao   Chen, Hsuan-an   Lee, Lun-ming   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   NATIONAL TAIWAN UNIVERSITY   IPC: H01L29/06 Abstract: A semiconductor device includes a substrate, semiconductor 2-D material layer, a conductive 2-D material layer, a gate dielectric layer, and a gate electrode. The semiconductor 2-D material layer is over the substrate. The conductive 2-D material layer extends along a source/drain region of the semiconductor 2-D material layer, in which the conductive 2-D material layer comprises a group-IV element. The gate dielectric layer extends along a channel region of the semiconductor 2-D material layer. The gate electrode is over the gate dielectric layer.
2
US2021005719A1
2D CRYSTAL HETERO-STRUCTURES AND MANUFACTURING METHODS THEREOF
Publication/Patent Number: US2021005719A1 Publication Date: 2021-01-07 Application Number: 17/027,237 Filing Date: 2020-09-21 Inventor: Lin shih yen   Lee, Si-chen   Pan, Samuel C.   Chen, Kuan-chao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L29/24 Abstract: A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.
3
US10985019B2
Method of forming a semiconductor device using layered etching and repairing of damaged portions
Publication/Patent Number: US10985019B2 Publication Date: 2021-04-20 Application Number: 16/859,822 Filing Date: 2020-04-27 Inventor: Lin shih yen   Chen, Kuan-chao   Lee, Si-chen   Pan, Samuel C.   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   NATIONAL TAIWAN UNIVERSITY   IPC: H01L27/115 Abstract: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.
4
US2020006541A1
SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALS
Publication/Patent Number: US2020006541A1 Publication Date: 2020-01-02 Application Number: 16/236,004 Filing Date: 2018-12-28 Inventor: Lin shih yen   Chen, Hsuan-an   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   National Taiwan University   IPC: H01L29/76 Abstract: The current disclosure describes semiconductor devices, e.g., transistors, including a substrate, a semiconductor region including, at the surface, monolayer MoS2 and/or other monolayer material over the substrate, and a terminal structure over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.
5
US10872973B2
Semiconductor structures with two-dimensional materials
Publication/Patent Number: US10872973B2 Publication Date: 2020-12-22 Application Number: 16/236,004 Filing Date: 2018-12-28 Inventor: Lin shih yen   Chen, Hsuan-an   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   National Taiwan University   IPC: H01L29/76 Abstract: The current disclosure describes semiconductor devices, e.g., transistors, including a substrate, a semiconductor region including, at the surface, monolayer MoS2 and/or other monolayer material over the substrate, and a terminal structure over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.
6
US202006541A1
SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALS
Publication/Patent Number: US202006541A1 Publication Date: 2020-01-02 Application Number: 20/181,623 Filing Date: 2018-12-28 Inventor: Lin shih yen   Chen, Hsuan-an   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   National Taiwan University   IPC: H01L29/76 Abstract: The current disclosure describes semiconductor devices, e.g., transistors, including a substrate, a semiconductor region including, at the surface, monolayer MoS2 and/or other monolayer material over the substrate, and a terminal structure over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.
7
US10541132B2
Forming semiconductor structures with two-dimensional materials
Publication/Patent Number: US10541132B2 Publication Date: 2020-01-21 Application Number: 16/005,363 Filing Date: 2018-06-11 Inventor: Lin shih yen   Chen, Hsuan-an   Lee, Si-chen   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   NATIONAL TAIWAN UNIVERSITY   IPC: H01L29/24 Abstract: The current disclosure describes semiconductor devices, e.g., transistors, include a substrate, a semiconductor region including, at the surface, MoS2 and/or other monolayer material over the substrate, and a terminal structure at least partially over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.
8
US2020194258A1
FORMING SEMICONDUCTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALS
Publication/Patent Number: US2020194258A1 Publication Date: 2020-06-18 Application Number: 16/712,570 Filing Date: 2019-12-12 Inventor: Lin shih yen   Chen, Hsuan-an   Lee, Si-chen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   National Taiwan University   IPC: H01L21/02 Abstract: The current disclosure describes semiconductor devices, e.g., transistors, include a substrate, a semiconductor region including, at the surface, MoS2 and/or other monolayer material over the substrate, and a terminal structure at least partially over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.
9
US10784351B2
2D crystal hetero-structures and manufacturing methods thereof
Publication/Patent Number: US10784351B2 Publication Date: 2020-09-22 Application Number: 15/868,282 Filing Date: 2018-01-11 Inventor: Lin shih yen   Lee, Si-chen   Pan, Samuel C.   Chen, Kuan-chao   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   NATIONAL TAIWAN UNIVERSITY   IPC: H01L29/24 Abstract: A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.
10
US10636652B2
Method of forming a semiconductor device using layered etching and repairing of damaged portions
Publication/Patent Number: US10636652B2 Publication Date: 2020-04-28 Application Number: 16/383,560 Filing Date: 2019-04-12 Inventor: Lin shih yen   Chen, Kuan-chao   Lee, Si-chen   Pan, Samuel C.   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   NATIONAL TAIWAN UNIVERSITY   IPC: H01L27/115 Abstract: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.
11
US2020266059A1
METHOD OF FORMING A SEMICONDUCTOR DEVICE USING LAYERED ETCHING AND REPAIRING OF DAMAGED PORTIONS
Publication/Patent Number: US2020266059A1 Publication Date: 2020-08-20 Application Number: 16/859,822 Filing Date: 2020-04-27 Inventor: Lin shih yen   Chen, Kuan-chao   Lee, Si-chen   Pan, Samuel C.   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   NATIONAL TAIWAN UNIVERSITY   IPC: H01L21/02 Abstract: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.
12
US10867835B2
Semiconductor packaging structure and process
Publication/Patent Number: US10867835B2 Publication Date: 2020-12-15 Application Number: 16/222,435 Filing Date: 2018-12-17 Inventor: Ho, Kuan-lin   Chen, Chin-liang   Lin, Wei-ting   Liu, Yu-chih   Lin shih yen   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/762 Abstract: A method and structure for packaging a semiconductor device are provided. In an embodiment a first substrate is bonded to a second substrate, which is bonded to a third substrate. A thermal interface material is placed on the second substrate prior to application of an underfill material. A ring can be placed on the thermal interface material, and an underfill material is dispensed between the second substrate and the third substrate. By placing the thermal interface material and ring prior to the underfill material, the underfill material cannot interfere with the interface between the thermal interface material and the second substrate, and the thermal interface material and ring can act as a physical barrier to the underfill material, thereby preventing overflow.
13
US10879140B2
System and method for bonding package lid
Publication/Patent Number: US10879140B2 Publication Date: 2020-12-29 Application Number: 16/227,247 Filing Date: 2018-12-20 Inventor: Lin shih yen   Liu, Yu-chih   Chen, Chin-liang   Lin, Wei-ting   Ho, Kuan-lin   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L23/10 Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
14
US10269902B2
Semiconductor device and method of formation
Publication/Patent Number: US10269902B2 Publication Date: 2019-04-23 Application Number: 15/852,391 Filing Date: 2017-12-22 Inventor: Lin, Meng-yu   Lin shih yen   Lee, Si-chen   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L29/16 Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
15
US2019378715A1
FORMING SEMICONDCUTOR STRUCTURES WITH TWO-DIMENSIONAL MATERIALS
Publication/Patent Number: US2019378715A1 Publication Date: 2019-12-12 Application Number: 16/005,363 Filing Date: 2018-06-11 Inventor: Lin shih yen   Chen, Hsuan-an   Lee, Si-chen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   National Taiwan University   IPC: H01L21/02 Abstract: The current disclosure describes semiconductor devices, e.g., transistors, include a substrate, a semiconductor region including, at the surface, MoS2 and/or other monolayer material over the substrate, and a terminal structure at least partially over the semiconductor region, which includes a different monolayer material grown directly over the semiconductor region.
16
US2019319101A1
SEMICONDUCTOR DEVICE AND METHOD OF FORMATION
Publication/Patent Number: US2019319101A1 Publication Date: 2019-10-17 Application Number: 16/390,364 Filing Date: 2019-04-22 Inventor: Lin, Meng-yu   Lin shih yen   Lee, Si-chen   Assignee: Taiwan Semiconductor Manufacturing Company Limited   IPC: H01L29/16 Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a substrate, a first active area over the substrate, a second active area over the substrate, a graphene channel between the first active area and the second active area, and a first in-plane gate. In some embodiments, the graphene channel, the first in-plane gate, the first active area, and the second active area include graphene. A method of forming the first in-plane gate, the first active area, the second active area, and the graphene channel from a single layer of graphene is also provided.
17
US10505052B2
Semiconductor device with transition metal dichalocogenide hetero-structure
Publication/Patent Number: US10505052B2 Publication Date: 2019-12-10 Application Number: 16/224,921 Filing Date: 2018-12-19 Inventor: Lin shih yen   Liu, Chi-wen   Wu, Chong-rong   Chang, Xiang-rui   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   National Taiwan University   IPC: H01L29/786 Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.
18
US2019123211A1
Semiconductor Device with Transition Metal Dichalocogenide Hetero-Structure
Publication/Patent Number: US2019123211A1 Publication Date: 2019-04-25 Application Number: 16/224,921 Filing Date: 2018-12-19 Inventor: Lin shih yen   Liu, Chi-wen   Wu, Chong-rong   Chang, Xiang-rui   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   National Taiwan University   IPC: H01L29/786 Abstract: A semiconductor device includes a first film disposed over a semiconductor substrate, the first film comprising a first transition metal dichalcogenide; a second film disposed over the first film, the second film comprising a second transition metal dichalcogenide different from the first transition metal dichalcogenide; source and drain features formed over the second film; a first gate stack formed over the second film and interposed between the source and drain features; and a second gate stack formed over the semiconductor substrate opposite from the first gate stack such that the semiconductor substrate is between the first and second gate stacks.
19
US10403744B2
Semiconductor devices comprising 2D-materials and methods of manufacture thereof
Publication/Patent Number: US10403744B2 Publication Date: 2019-09-03 Application Number: 14/753,851 Filing Date: 2015-06-29 Inventor: Lin shih yen   Pan, Samuel C.   Wu, Chong-rong   Chang, Xian-rui   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   National Taiwan University   IPC: H01L21/786 Abstract: A method for manufacturing a semiconductor device comprising two-dimensional (2D) materials may include: epitaxially forming a first two-dimensional (2D) material layer over a substrate; calculating a mean thickness of the first 2D material layer; comparing the mean thickness of the first 2D material layer with a reference parameter; determining that the mean thickness of the first 2D material layer is not substantially equal to the reference parameter; and after the determining, epitaxially forming a second 2D material layer over the first 2D material layer.
20
US10269668B2
System and method for bonding package lid
Publication/Patent Number: US10269668B2 Publication Date: 2019-04-23 Application Number: 15/613,815 Filing Date: 2017-06-05 Inventor: Lin shih yen   Liu, Yu-chih   Chen, Chin-liang   Lin, Wei-ting   Ho, Kuan-lin   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/44 Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
Total 5 pages