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1
US2021013033A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2021013033A1 Publication Date: 2021-01-14 Application Number: 17/036,734 Filing Date: 2020-09-29 Inventor: Chang, Cheng-wei   Hung, Min-hsiu   Huang, Hung-yi   Wang, Chun Chieh   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
2
US2020119152A1
Low Resistant Contact Method and Structure
Publication/Patent Number: US2020119152A1 Publication Date: 2020-04-16 Application Number: 16/715,927 Filing Date: 2019-12-16 Inventor: Wang, Yu-sheng   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/417 Abstract: A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.
3
US10588932B2
Method for promoting hair growth using banana stamen extract
Publication/Patent Number: US10588932B2 Publication Date: 2020-03-17 Application Number: 16/174,948 Filing Date: 2018-10-30 Inventor: Lin yu ting   Lin, Yung-hsiang   Assignee: TCI CO., LTD.   IPC: A61Q7/00 Abstract: The present invention relates to a use of a banana stamen extract for promoting hair growth. The banana stamen extract according to the present invention promotes gene expression of VEGF and IGF1 to enhance the proliferation level of hair follicles, so that the density of hairs grown is increased. In addition, the banana stamen extract also inhibits gene expression of SRD5A1, SRDA2 and AR to decrease hair loss, and promote the gene expression of KROX20 so as to significantly enhance hair growth.
4
US2020337402A1
TRY-ON ASSISTANT DEVICE, SYSTEM, AND METHOD
Publication/Patent Number: US2020337402A1 Publication Date: 2020-10-29 Application Number: 16/527,656 Filing Date: 2019-07-31 Inventor: Lin yu ting   Tsai, Jewel   Assignee: Chicony Power Technology Co., Ltd.   IPC: A41H1/02 Abstract: A try-on assistant device is provided for simulating to-be-tried-on apparel. The to-be-tried-on apparel includes a measurement area, and the try-on assistant device includes a model suit, an airbag group, an inflating/deflating unit, and a control unit. The model suit includes a simulation part corresponding to the measurement area. The airbag group includes a plurality of airbags, where the airbags are disposed on the simulation part of the model suit. The inflating/deflating unit is configured to separately inflate or deflate the plurality of airbags. The control unit controls, according to an inflating/deflating parameter, the inflating/deflating unit to inflate or deflate some or all of the airbags, where the inflating/deflating parameter corresponds to size information of the measurement area of the to-be-tried-on apparel.
5
US2020321484A1
PN JUNCTION AND PREPARATION METHOD AND USE THEREOF
Publication/Patent Number: US2020321484A1 Publication Date: 2020-10-08 Application Number: 16/837,189 Filing Date: 2020-04-01 Inventor: Gao, Liang   Zhang, Zhun   Lin yu ting   Assignee: Sunflare (Nanjing) Energy Technology Ltd   IPC: H01L31/032 Abstract: The patent application relates to a PN junction as well as the preparation method and use thereof. Said PN junction comprises a p-type CIGS semiconductor thin film layer and an n-type CIGS semiconductor thin film layer, wherein the n-type CIGS semiconductor thin film layer comprises or consists essentially of elements Cu, In, Ga and Se, where the Cu to In molar ratio is within the range of 1.1 to 1.5, and has a chemical formula of Cu(InxGa1-x)Se2, where x is within the range of 0.6 to 0.9. The patent application further relates to a semiconductor thin film element comprising said PN junction, in particular a photodiode element, and a photoelectric sensing module comprising said semiconductor thin film element as well as the various uses thereof.
6
EP3719854A1
PN JUNCTION AND PREPARATION METHOD AND USE THEREOF
Publication/Patent Number: EP3719854A1 Publication Date: 2020-10-07 Application Number: 20167490.0 Filing Date: 2020-04-01 Inventor: Gao, Liang   Zhang, Zhun   Lin yu ting   Assignee: Sunflare (Nanjing) Energy Technology Ltd.   IPC: H01L31/032 Abstract: The patent application relates to a PN junction as well as the preparation method and use thereof. Said PN junction comprises a p-type CIGS semiconductor thin film layer and an n-type CIGS semiconductor thin film layer, wherein the n-type CIGS semiconductor thin film layer comprises or consists essentially of elements Cu, In, Ga and Se, where the Cu to In molar ratio is within the range of 1.1 to 1.5, and has a chemical formula of Cu(InxGa1. x)Se2, where x is within the range of 0.6 to 0.9. The patent application further relates to a semiconductor thin film element comprising said PN junction, in particular a photodiode element, and a photoelectric sensing module comprising said semiconductor thin film element as well as the various uses thereof.
7
US2020301509A1
SYSTEM FOR RECOGNIZING USER GESTURES ACCORDING TO MECHANOMYOGRAM DETECTED FROM USER'S WRIST AND METHOD THEREOF
Publication/Patent Number: US2020301509A1 Publication Date: 2020-09-24 Application Number: 16/822,344 Filing Date: 2020-03-18 Inventor: Liu, Meng Kun   Qiu, Zhao Wei   Lin, Yu Ting   Kuo, Chao Kuang   Wu, Chi Kang   Assignee: Coolso Technology Inc.   IPC: G06F3/01 Abstract: A system for recognizing user gestures according to a muscle active signal detected from the user's wrist and a method thereof are provided. After detecting a target muscle active signal from a wrist of a user, the system obtains a target feature signal when the measured amplitude exceeds a predetermined value of the target muscle active signal, generates target feature data in accordance with the target feature signal, and uses a gesture classification model to classify the target feature data for recognizing the user's gestures. The proposed system and the method can let users easily wear this muscle active signal detecting device at the correct position for recognizing gestures accurately, and can achieve the effect of recognizing gestures with lower power consumption and lower costs.
8
EP3165960B1
DISPLAY APPARATUS
Publication/Patent Number: EP3165960B1 Publication Date: 2020-03-25 Application Number: 16196056.2 Filing Date: 2016-10-27 Inventor: Liu, Chin-ku   Hsu, Huai-chung   Lin yu ting   Wu, Jhong-hao   Assignee: Champ Vision Display Inc.   IPC: G02F1/1333
9
US2020064396A1
METHOD AND SYSTEM FOR WAFER-LEVEL TESTING
Publication/Patent Number: US2020064396A1 Publication Date: 2020-02-27 Application Number: 16/522,551 Filing Date: 2019-07-25 Inventor: He, Jun   Lin yu ting   Lin, Wei-hsun   Kuo, Yung-liang   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: G01R31/28 Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
10
US2020052126A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2020052126A1 Publication Date: 2020-02-13 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Lin yu ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
11
US2020006058A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2020006058A1 Publication Date: 2020-01-02 Application Number: 16/568,720 Filing Date: 2019-09-12 Inventor: Chang, Cheng-wei   Hung, Min-hsiu   Huang, Huang-yi   Wang, Chun-chieh   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
12
US202052126A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US202052126A1 Publication Date: 2020-02-13 Application Number: 20/191,665 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Yang, Huai-tei   Lin yu ting   Chang, Shih-chieh   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
13
US2020286777A1
INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
Publication/Patent Number: US2020286777A1 Publication Date: 2020-09-10 Application Number: 16/389,644 Filing Date: 2019-04-19 Inventor: Wang, Mao-ying   Shih, Shing-yih   Wu, Hung-mo   Ting, Yung-te   Lin yu ting   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: The present disclosure provides a method for preparing an interconnect structure. One aspect of the present disclosure provides a method for preparing an interconnect structure. The method includes the following steps. A first dielectric layer is provided over a first connecting line. A first upper via opening is formed in the first dielectric layer, wherein the first upper via opening has a first width. A first lower via opening is formed in the first dielectric layer, wherein the first lower via opening is formed under and coupled to the first upper via opening. The first lower via opening has a second width less than the first width of the first upper via opening. A connecting via is formed in the first upper via opening and the first lower via opening. A second connecting line is formed over the connecting via.
14
US202006058A1
Conductive Feature Formation and Structure
Publication/Patent Number: US202006058A1 Publication Date: 2020-01-02 Application Number: 20/191,656 Filing Date: 2019-09-12 Inventor: Wang, Chun-chieh   Lin yu ting   Chang, Cheng-wei   Huang, Huang-yi   Hung, Min-hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
15
US10714334B2
Conductive feature formation and structure
Publication/Patent Number: US10714334B2 Publication Date: 2020-07-14 Application Number: 15/860,354 Filing Date: 2018-01-02 Inventor: Chang, Cheng-wei   Huang, Huang-yi   Wang, Chun-chieh   Lin yu ting   Hung, Min-hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/762 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
16
US10804097B2
Conductive feature formation and structure
Publication/Patent Number: US10804097B2 Publication Date: 2020-10-13 Application Number: 16/568,720 Filing Date: 2019-09-12 Inventor: Chang, Cheng-wei   Hung, Min-hsiu   Huang, Hung-yi   Wang, Chun Chieh   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
17
US2020176377A1
ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME
Publication/Patent Number: US2020176377A1 Publication Date: 2020-06-04 Application Number: 16/251,858 Filing Date: 2019-01-18 Inventor: Lin yu ting   Wang, Mao-ying   Shih, Shing-yih   Wu, Hung-mo   Ting, Yung-te   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L23/522 Abstract: The present disclosure provides an electronic device and a method of manufacturing the same. The electronic device includes a multilayer component, at least one contact pad, a passivation layer, a dielectric layer, and a metallic layer. The contact pad is disposed on the multilayer component, the passivation layer covers the multilayer component and the contact pad, and the dielectric layer is disposed on the passivation layer. The metallic layer penetrates through the dielectric layer and the passivation layer and is connected to the contact pad, and the metallic layer discretely tapers at positions of decreasing distance from the contact pad.
18
US2020286775A1
INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME
Publication/Patent Number: US2020286775A1 Publication Date: 2020-09-10 Application Number: 16/291,376 Filing Date: 2019-03-04 Inventor: Wang, Mao-ying   Shih, Shing-yih   Wu, Hung-mo   Ting, Yung-te   Lin yu ting   Assignee: NANYA TECHNOLOGY CORPORATION   IPC: H01L21/768 Abstract: The present disclosure provides an interconnect structure. The interconnect structure includes a first connecting line, a second connecting line disposed over the first connecting line, and a connecting via disposed in a dielectric structure between the first connecting line and the second connecting line, and electrically connecting the first connecting line and the second connecting line. The connecting via includes a head portion and a body portion, and a width of the head portion is greater than a width of the body portion.
19
US10685842B2
Selective formation of titanium silicide and titanium nitride by hydrogen gas control
Publication/Patent Number: US10685842B2 Publication Date: 2020-06-16 Application Number: 15/983,216 Filing Date: 2018-05-18 Inventor: Chang, Cheng-wei   Lin, Kao-feng   Hung, Min-hsiu   Chao, Yi-hsiang   Huang, Huang-yi   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/285 Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
20
US10867845B2
Semiconductor device and method
Publication/Patent Number: US10867845B2 Publication Date: 2020-12-15 Application Number: 16/599,940 Filing Date: 2019-10-11 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou, Yang Liang-yueh   Tsai, Ming-hsing   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
Total 26 pages