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1
US2021162090A1
COMPOSITE FIBER
Publication/Patent Number: US2021162090A1 Publication Date: 2021-06-03 Application Number: 16/699,138 Filing Date: 2019-11-29 Inventor: Hu, Wei-wen   Lin yu ting   Assignee: National Central University   IPC: A61L15/22 Abstract: The present invention provides a composite fiber which comprises an alginate fiber, a polymer material, an antibacterial agent, and a plasmid encoding growth factor-gene. The present invention also provides a wound dressing, wherein the wound dressing comprises a composite fiber as described above. The composite fibers prepared according to the present invention are capable of releasing the antibacterial agent and the growth factor gene, not only to reduce microorganism growth, but also to secrete growth factors in a wound site through transfection, thereby promoting wound healing.
2
US11020445B2
Method for reducing the content of heavy metals in blood and improving the pulmonary function using green pear fruitlet extract
Publication/Patent Number: US11020445B2 Publication Date: 2021-06-01 Application Number: 16/174,573 Filing Date: 2018-10-30 Inventor: Lin, Yung-hsiang   Lin yu ting   Assignee: TCI CO., LTD.   IPC: A61K36/73 Abstract: The present invention provides a method for reducing the content of heavy metals in blood and improving the pulmonary function using green pear fruitlet extract. The green pear fruitlet extract can effectively reduce the content of harmful heavy metals in human body to prevent the harmful effects of heavy metals, and improve forced vital capacity and the peak expiratory flow of humans to reduce the respiratory resistance and increase the expiratory flow. The green pear fruitlet extract is prepared by extracting green pear fruitlet using water, alcohol, or a mixture of water and alcohol as a solvent.
3
US11023045B2
System for recognizing user gestures according to mechanomyogram detected from user's wrist and method thereof
Publication/Patent Number: US11023045B2 Publication Date: 2021-06-01 Application Number: 16/822,344 Filing Date: 2020-03-18 Inventor: Liu, Meng Kun   Qiu, Zhao Wei   Lin, Yu Ting   Kuo, Chao Kuang   Wu, Chi Kang   Assignee: COOLSO TECHNOLOGY INC.   IPC: G09G5/00 Abstract: A system for recognizing user gestures according to a muscle active signal detected from the user's wrist and a method thereof are provided. After detecting a target muscle active signal from a wrist of a user, the system obtains a target feature signal when the measured amplitude exceeds a predetermined value of the target muscle active signal, generates target feature data in accordance with the target feature signal, and uses a gesture classification model to classify the target feature data for recognizing the user's gestures. The proposed system and the method can let users easily wear this muscle active signal detecting device at the correct position for recognizing gestures accurately, and can achieve the effect of recognizing gestures with lower power consumption and lower costs.
4
US2021080823A1
Pellicle and Method of Manufacturing Same
Publication/Patent Number: US2021080823A1 Publication Date: 2021-03-18 Application Number: 16/573,850 Filing Date: 2019-09-17 Inventor: Li, Po Hsuan   Lin yu ting   Lin, Yun-yue   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: G03F1/62 Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.
5
US10937910B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Publication/Patent Number: US10937910B2 Publication Date: 2021-03-02 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Lin yu ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
6
US2021013033A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2021013033A1 Publication Date: 2021-01-14 Application Number: 17/036,734 Filing Date: 2020-09-29 Inventor: Chang, Cheng-wei   Hung, Min-hsiu   Huang, Hung-yi   Wang, Chun Chieh   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
7
US10964590B2
Contact metallization process
Publication/Patent Number: US10964590B2 Publication Date: 2021-03-30 Application Number: 15/967,056 Filing Date: 2018-04-30 Inventor: Chou, Tien-pei   Chang, Ken-yu   Lin, Sheng-hsuan   Pai, Yueh-ching   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.
8
US2021143278A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2021143278A1 Publication Date: 2021-05-13 Application Number: 17/155,467 Filing Date: 2021-01-22 Inventor: Wang, Chun-chieh   Lin yu ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.
9
US10588932B2
Method for promoting hair growth using banana stamen extract
Publication/Patent Number: US10588932B2 Publication Date: 2020-03-17 Application Number: 16/174,948 Filing Date: 2018-10-30 Inventor: Lin yu ting   Lin, Yung-hsiang   Assignee: TCI CO., LTD.   IPC: A61Q7/00 Abstract: The present invention relates to a use of a banana stamen extract for promoting hair growth. The banana stamen extract according to the present invention promotes gene expression of VEGF and IGF1 to enhance the proliferation level of hair follicles, so that the density of hairs grown is increased. In addition, the banana stamen extract also inhibits gene expression of SRD5A1, SRDA2 and AR to decrease hair loss, and promote the gene expression of KROX20 so as to significantly enhance hair growth.
10
US2020337402A1
TRY-ON ASSISTANT DEVICE, SYSTEM, AND METHOD
Publication/Patent Number: US2020337402A1 Publication Date: 2020-10-29 Application Number: 16/527,656 Filing Date: 2019-07-31 Inventor: Lin yu ting   Tsai, Jewel   Assignee: Chicony Power Technology Co., Ltd.   IPC: A41H1/02 Abstract: A try-on assistant device is provided for simulating to-be-tried-on apparel. The to-be-tried-on apparel includes a measurement area, and the try-on assistant device includes a model suit, an airbag group, an inflating/deflating unit, and a control unit. The model suit includes a simulation part corresponding to the measurement area. The airbag group includes a plurality of airbags, where the airbags are disposed on the simulation part of the model suit. The inflating/deflating unit is configured to separately inflate or deflate the plurality of airbags. The control unit controls, according to an inflating/deflating parameter, the inflating/deflating unit to inflate or deflate some or all of the airbags, where the inflating/deflating parameter corresponds to size information of the measurement area of the to-be-tried-on apparel.
11
US2020119152A1
Low Resistant Contact Method and Structure
Publication/Patent Number: US2020119152A1 Publication Date: 2020-04-16 Application Number: 16/715,927 Filing Date: 2019-12-16 Inventor: Wang, Yu-sheng   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/417 Abstract: A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.
12
EP3719854A1
PN JUNCTION AND PREPARATION METHOD AND USE THEREOF
Publication/Patent Number: EP3719854A1 Publication Date: 2020-10-07 Application Number: 20167490.0 Filing Date: 2020-04-01 Inventor: Gao, Liang   Zhang, Zhun   Lin yu ting   Assignee: Sunflare (Nanjing) Energy Technology Ltd.   IPC: H01L31/032 Abstract: The patent application relates to a PN junction as well as the preparation method and use thereof. Said PN junction comprises a p-type CIGS semiconductor thin film layer and an n-type CIGS semiconductor thin film layer, wherein the n-type CIGS semiconductor thin film layer comprises or consists essentially of elements Cu, In, Ga and Se, where the Cu to In molar ratio is within the range of 1.1 to 1.5, and has a chemical formula of Cu(InxGa1. x)Se2, where x is within the range of 0.6 to 0.9. The patent application further relates to a semiconductor thin film element comprising said PN junction, in particular a photodiode element, and a photoelectric sensing module comprising said semiconductor thin film element as well as the various uses thereof.
13
US2020321484A1
PN JUNCTION AND PREPARATION METHOD AND USE THEREOF
Publication/Patent Number: US2020321484A1 Publication Date: 2020-10-08 Application Number: 16/837,189 Filing Date: 2020-04-01 Inventor: Gao, Liang   Zhang, Zhun   Lin yu ting   Assignee: Sunflare (Nanjing) Energy Technology Ltd   IPC: H01L31/032 Abstract: The patent application relates to a PN junction as well as the preparation method and use thereof. Said PN junction comprises a p-type CIGS semiconductor thin film layer and an n-type CIGS semiconductor thin film layer, wherein the n-type CIGS semiconductor thin film layer comprises or consists essentially of elements Cu, In, Ga and Se, where the Cu to In molar ratio is within the range of 1.1 to 1.5, and has a chemical formula of Cu(InxGa1-x)Se2, where x is within the range of 0.6 to 0.9. The patent application further relates to a semiconductor thin film element comprising said PN junction, in particular a photodiode element, and a photoelectric sensing module comprising said semiconductor thin film element as well as the various uses thereof.
14
US2020301509A1
SYSTEM FOR RECOGNIZING USER GESTURES ACCORDING TO MECHANOMYOGRAM DETECTED FROM USER'S WRIST AND METHOD THEREOF
Publication/Patent Number: US2020301509A1 Publication Date: 2020-09-24 Application Number: 16/822,344 Filing Date: 2020-03-18 Inventor: Liu, Meng Kun   Qiu, Zhao Wei   Lin, Yu Ting   Kuo, Chao Kuang   Wu, Chi Kang   Assignee: Coolso Technology Inc.   IPC: G06F3/01 Abstract: A system for recognizing user gestures according to a muscle active signal detected from the user's wrist and a method thereof are provided. After detecting a target muscle active signal from a wrist of a user, the system obtains a target feature signal when the measured amplitude exceeds a predetermined value of the target muscle active signal, generates target feature data in accordance with the target feature signal, and uses a gesture classification model to classify the target feature data for recognizing the user's gestures. The proposed system and the method can let users easily wear this muscle active signal detecting device at the correct position for recognizing gestures accurately, and can achieve the effect of recognizing gestures with lower power consumption and lower costs.
15
EP3165960B1
DISPLAY APPARATUS
Publication/Patent Number: EP3165960B1 Publication Date: 2020-03-25 Application Number: 16196056.2 Filing Date: 2016-10-27 Inventor: Liu, Chin-ku   Hsu, Huai-chung   Lin yu ting   Wu, Jhong-hao   Assignee: Champ Vision Display Inc.   IPC: G02F1/1333
16
US2020064396A1
METHOD AND SYSTEM FOR WAFER-LEVEL TESTING
Publication/Patent Number: US2020064396A1 Publication Date: 2020-02-27 Application Number: 16/522,551 Filing Date: 2019-07-25 Inventor: He, Jun   Lin yu ting   Lin, Wei-hsun   Kuo, Yung-liang   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: G01R31/28 Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
17
US2020052126A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2020052126A1 Publication Date: 2020-02-13 Application Number: 16/654,175 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Lin yu ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
18
US2020006058A1
Conductive Feature Formation and Structure
Publication/Patent Number: US2020006058A1 Publication Date: 2020-01-02 Application Number: 16/568,720 Filing Date: 2019-09-12 Inventor: Chang, Cheng-wei   Hung, Min-hsiu   Huang, Huang-yi   Wang, Chun-chieh   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
19
US202052126A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US202052126A1 Publication Date: 2020-02-13 Application Number: 20/191,665 Filing Date: 2019-10-16 Inventor: Wang, Chun-chieh   Yang, Huai-tei   Lin yu ting   Chang, Shih-chieh   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
20
US202006058A1
Conductive Feature Formation and Structure
Publication/Patent Number: US202006058A1 Publication Date: 2020-01-02 Application Number: 20/191,656 Filing Date: 2019-09-12 Inventor: Wang, Chun-chieh   Lin yu ting   Chang, Cheng-wei   Huang, Huang-yi   Hung, Min-hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L23/532 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
Total 26 pages