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61
US10453933B2
Barrier layer for dielectric layers in semiconductor devices
Publication/Patent Number: US10453933B2 Publication Date: 2019-10-22 Application Number: 15/336,136 Filing Date: 2016-10-27 Inventor: Chen, Sheng-wen   Lin yu ting   Chang, Che-hao   You, Wei-ming   Wang, Ting-chun   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L29/40 Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.
62
US2019148556A1
SEMICONDUCTOR STRUCTURE WITH SOURCE/DRAIN MULTI-LAYER STRUCTURE AND METHOD FOR FORMING THE SAME
Publication/Patent Number: US2019148556A1 Publication Date: 2019-05-16 Application Number: 16/043,371 Filing Date: 2018-07-24 Inventor: Wang, Chun-chieh   Lin yu ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.
63
TWI675197B
GAS-SENSING APPARATUS
Publication/Patent Number: TWI675197B Publication Date: 2019-10-21 Application Number: 107147397 Filing Date: 2018-12-27 Inventor: Lin yu ting   Meng, Hsin-fei   Yeh, Ping-hung   Zan, Hsiao-wen   Lu, Chia-jung   Assignee: National Chiao Tung University   IPC: G01N27/407
64
US2019148223A1
CONTACT METALLIZATION PROCESS
Publication/Patent Number: US2019148223A1 Publication Date: 2019-05-16 Application Number: 15/967,056 Filing Date: 2018-04-30 Inventor: Chou, Tien-pei   Chang, Ken-yu   Lin, Sheng-hsuan   Pai, Yueh-ching   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.
65
TW201923975A
Method of forming semiconductor structure
Publication/Patent Number: TW201923975A Publication Date: 2019-06-16 Application Number: 107137954 Filing Date: 2018-10-26 Inventor: Lin yu ting   Lin, Sheng-hsuan   Pai, Yueh-ching   Chang, Ken-yu   Chou, Tien-pei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure describes a method to a metallization process with improved gap fill properties. The method includes forming a contact opening in an oxide, forming a barrier layer in the contact opening, forming a liner layer on the barrier layer, and forming a first metal layer on the liner layer to partially fill the contact opening. The method further includes forming a second metal layer on the first metal layer to fill the contact opening, where forming the second metal layer includes sputter depositing the second metal layer with a first radio frequency (RF) power and a direct current power, as well as reflowing the second metal layer with a second RF power.
66
TW201924061A
Semiconductor structure
Publication/Patent Number: TW201924061A Publication Date: 2019-06-16 Application Number: 107137353 Filing Date: 2018-10-23 Inventor: Lin yu ting   Chang, Shih-chieh   Wang, Chun-chieh   Yang, Huai-tei   Pai, Yueh-ching   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L29/772 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.
67
US10468530B2
Semiconductor structure with source/drain multi-layer structure and method for forming the same
Publication/Patent Number: US10468530B2 Publication Date: 2019-11-05 Application Number: 16/043,371 Filing Date: 2018-07-24 Inventor: Wang, Chun-chieh   Lin yu ting   Pai, Yueh-ching   Chang, Shih-chieh   Yang, Huai-tei   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.   IPC: H01L29/78 Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.
68
US2019164747A1
CONDUCTIVE FEATURE FORMATION AND STRUCTURE
Publication/Patent Number: US2019164747A1 Publication Date: 2019-05-30 Application Number: 15/860,354 Filing Date: 2018-01-02 Inventor: Chang, Cheng-wei   Huang, Huang-yi   Wang, Chun-chieh   Lin yu ting   Hung, Min-hsiu   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/02 Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In a method embodiment, a dielectric layer is formed on a semiconductor substrate. The semiconductor substrate has a source/drain region. An opening is formed through the dielectric layer to the source/drain region. A silicide region is formed on the source/drain region and a barrier layer is formed in the opening along sidewalls of the dielectric layer by a same Plasma-Enhance Chemical Vapor Deposition (PECVD) process.
69
TWM586819U
APP application producing platform structure
Publication/Patent Number: TWM586819U Publication Date: 2019-11-21 Application Number: 108204546 Filing Date: 2019-04-12 Inventor: Lin yu ting   Li, Shu-min   Liu, Feng-ming   Su, Sheng-zhu   Liu, Pei-ying   Assignee: HWA HSIA UNIVERSITY OF TECHNOLOGY   IPC: G06F17/00
70
US2019164822A1
Semiconductor Device With TiN Adhesion Layer For Forming A Contact Plug
Publication/Patent Number: US2019164822A1 Publication Date: 2019-05-30 Application Number: 15/887,819 Filing Date: 2018-02-02 Inventor: Chou, Tien-pei   Chang, Ken-yu   Wang, Chun-chieh   Pai, Yueh-ching   Lin yu ting   Cheng, Yu-wen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.
71
TWI652028B
Nursing mattress, nursing bed and nursing bed system characterized in that the nursing bed can provide appropriate supporting and wrapping performance of the nesting and positioning care according to the body figure and prone posture of premature baby
Publication/Patent Number: TWI652028B Publication Date: 2019-03-01 Application Number: 106141906 Filing Date: 2017-11-30 Inventor: Lin yu ting   An, Nai-jun   Lin, Yuan-zhi   Wu, Feng-guang   Chen, Shuo-qing   Lin, Qi-he   Zhang, Ying-ru   Gao, Hui-mei   Assignee: National Cheng Kung University   Metal Industries Research & Development Centre   IPC: A47D15/00 Abstract: Disclosed are a nursing mattress, a nursing bed and a nursing bed system. The nursing mattress is installed with a plurality of supporting pad bodies distributed in a mattress main body thereof. The nursing bed is installed with the nursing mattress at a bed base thereof. A plurality of supporting mechanisms are installed in the bed base and are electrically connected to an operating device. The nursing bed system includes a nursing bed, a sensing module and a central control module. The sensing module includes a plurality of force sensors and a measuring device. The force sensors are electrically connected to the measuring device. The central control module is connected to the measuring device and the operating device, so that the central control module can immediately record, monitor and sense the data, accumulate the big data of the nursing and control the operating device to change the position and height of the supporting pad bodies. Therefore, the nursing bed can provide appropriate supporting and wrapping performance of the nesting and positioning care according to the body figure and prone posture of a premature baby.
72
TW201924585A
Nursing mattress, nursing bed and nursing bed system characterized in that the nursing bed can provide appropriate supporting and wrapping performance of the nesting and positioning care according to the body figure and prone posture of premature baby
Publication/Patent Number: TW201924585A Publication Date: 2019-07-01 Application Number: 106141906 Filing Date: 2017-11-30 Inventor: Lin yu ting   An, Nai-jun   Lin, Yuan-zhi   Wu, Feng-guang   Chen, Shuo-qing   Lin, Qi-he   Zhang, Ying-ru   Gao, Hui-mei   Assignee: National Cheng Kung University   Metal Industries Research & Development Centre   IPC: A47D15/00 Abstract: Disclosed are a nursing mattress, a nursing bed and a nursing bed system. The nursing mattress is installed with a plurality of supporting pad bodies distributed in a mattress main body thereof. The nursing bed is installed with the nursing mattress at a bed base thereof. A plurality of supporting mechanisms are installed in the bed base and are electrically connected to an operating device. The nursing bed system includes a nursing bed, a sensing module and a central control module. The sensing module includes a plurality of force sensors and a measuring device. The force sensors are electrically connected to the measuring device. The central control module is connected to the measuring device and the operating device, so that the central control module can immediately record, monitor and sense the data, accumulate the big data of the nursing and control the operating device to change the position and height of the supporting pad bodies. Therefore, the nursing bed can provide appropriate supporting and wrapping performance of the nesting and positioning care according to the body figure and prone posture of a premature baby.
73
TW201926558A
Method for manufacturing semiconductor device
Publication/Patent Number: TW201926558A Publication Date: 2019-07-01 Application Number: 107124087 Filing Date: 2018-07-12 Inventor: Lin yu ting   Wang, Chun-chieh   Cheng, Yu-wen   Pai, Yueh-ching   Chang, Ken-yu   Chou, Tien-pei   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.
74
US10332789B2
Semiconductor device with TiN adhesion layer for forming a contact plug
Publication/Patent Number: US10332789B2 Publication Date: 2019-06-25 Application Number: 15/887,819 Filing Date: 2018-02-02 Inventor: Chou, Tien-pei   Chang, Ken-yu   Wang, Chun-chieh   Pai, Yueh-ching   Lin yu ting   Cheng, Yu-wen   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/768 Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.
75
US2019355585A1
SELECTIVE FORMATION OF TITANIUM SILICIDE AND TITANIUM NITRIDE BY HYDROGEN GAS CONTROL
Publication/Patent Number: US2019355585A1 Publication Date: 2019-11-21 Application Number: 15/983,216 Filing Date: 2018-05-18 Inventor: Chang, Cheng-wei   Lin, Kao-feng   Hung, Min-hsiu   Chao, Yi-hsiang   Huang, Huang-yi   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.   IPC: H01L21/285 Abstract: The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.
76
US10522631B2
Contact silicide having a non-angular profile
Publication/Patent Number: US10522631B2 Publication Date: 2019-12-31 Application Number: 16/042,287 Filing Date: 2018-07-23 Inventor: Chen, Sheng-wen   Yu-shen, Shih   Lo, Chia Ping   Lin, Yan-hua   Tan, Lun-kuang   Lin yu ting   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.   IPC: H01L29/417 Abstract: A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.
77
US2019109043A1
Semiconductor Device and Method
Publication/Patent Number: US2019109043A1 Publication Date: 2019-04-11 Application Number: 16/213,868 Filing Date: 2018-12-07 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou, Yang Liang-yueh   Tsai, Ming-hsing   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
78
US10497615B2
Semiconductor device and method
Publication/Patent Number: US10497615B2 Publication Date: 2019-12-03 Application Number: 16/213,868 Filing Date: 2018-12-07 Inventor: Wang, Yu-sheng   Hung, Chi-cheng   Su, Ching-hwanq   Ou, Yang Liang-yueh   Tsai, Ming-hsing   Lin yu ting   Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.   IPC: H01L21/768 Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.
79
TWM577669U
Smart key ring
Publication/Patent Number: TWM577669U Publication Date: 2019-05-11 Application Number: 107217401 Filing Date: 2018-12-21 Inventor: Lin yu ting   Chen, Li-heng   Liu, Ming-wei   Xu, Ting-xuan   Hou, Ya-yu   Liao, Yuan-hao   Tang, Jing   Chen, Xin-kai   Ruan, Sheng-you   Cai, Yun-lin   Assignee: WU SHAN ELEMENTARY SCHOOL   IPC: G10L17/00
80
US10216744B2
Data migration to a cloud computing system
Publication/Patent Number: US10216744B2 Publication Date: 2019-02-26 Application Number: 14/854,798 Filing Date: 2015-09-15 Inventor: Yap, Joe Keng   Thangaraju, Mahadevan   Livingston, Sean L.   Cannerozzi, Roberta   Moussa, Ghania   Estrin, Ron Shimon   Lin yu ting   Bourdages, Simon   Nguyen, Trung Duc   Cai, Wenyu   Koehne, Zachary Adam   Simek, Patrick J.   Gulati, Sukhvinder Singh   Canning, Ben   Assignee: Microsoft Technology Licensing, LLC   IPC: G06F17/30 Abstract: A cloud-based migration system exposes a source-independent application programming interface for receiving data to be migrated. The data is uploaded and stored as a single entity in a cloud-based storage system. A migration system then accesses the migration package and begins migrating the data to its destination, from the cloud-based storage system.
Total 26 pages