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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US2021119634A1
SUB-SAMPLING PHASE-LOCKED LOOP
Publication/Patent Number: US2021119634A1 Publication Date: 2021-04-22 Application Number: 17/075,651 Filing Date: 2020-10-20 Inventor: Yang, Yu-che   Chan, Ka-un   Lu, Yong-ru   Liu shen iuan   Assignee: Realtek Semiconductor Corp.   IPC: H03L7/093 Abstract: The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.
2
US10725486B2
Reference voltage generator
Publication/Patent Number: US10725486B2 Publication Date: 2020-07-28 Application Number: 16/052,654 Filing Date: 2018-08-02 Inventor: Fang, Yong-ren   Liu shen iuan   Huang, Ju-lin   Tzeng, Tzu-chien   Liang, Keko-chun   Wang, Yu-hsiang   Yeh, Che-wei   Assignee: Novatek Microelectronics Corp.   IPC: G05F1/46 Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.
3
US10594264B2
Dynamic amplifier and related gain boosting method
Publication/Patent Number: US10594264B2 Publication Date: 2020-03-17 Application Number: 16/021,032 Filing Date: 2018-06-28 Inventor: Huang, Ju-lin   Huang, Kuo-sheng   Lin, Jin-yi   Tzeng, Tzu-chien   Liu shen iuan   Hsieh, Cheng-en   Assignee: NOVATEK Microelectronics Corp.   IPC: H03K19/0185 Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.
4
US2020007085A1
Dynamic amplifier and related gain boosting method
Publication/Patent Number: US2020007085A1 Publication Date: 2020-01-02 Application Number: 16/021,032 Filing Date: 2018-06-28 Inventor: Hsieh, Cheng-en   Liu shen iuan   Tzeng, Tzu-chien   Lin, Jin-yi   Huang, Kuo-sheng   Huang, Ju-lin   Assignee: NOVATEK Microelectronics Corp.   IPC: H03F1/02 Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.
5
US202007085A1
Dynamic amplifier and related gain boosting method
Publication/Patent Number: US202007085A1 Publication Date: 2020-01-02 Application Number: 20/181,602 Filing Date: 2018-06-28 Inventor: Liu shen iuan   Tzeng, Tzu-chien   Huang, Ju-lin   Hsieh, Cheng-en   Huang, Kuo-sheng   Lin, Jin-yi   Assignee: Novatek Microelectronics Corp.   IPC: H03F1/02 Abstract: A dynamic amplifier includes a first output capacitor, a first switch, a current source, a second switch, a voltage detector, a third switch and a level shifter. The first switch is coupled between a first terminal of the first output capacitor and a voltage detection node. The second switch is coupled to the current source and the voltage detection node. The voltage detector is coupled to the voltage detection node and the first switch. The third switch is coupled between the voltage detection node and a power source. The level shifter is coupled to a second terminal of the first output capacitor.
6
US10256967B2
Clock and data recovery circuit with jitter tolerance enhancement
Publication/Patent Number: US10256967B2 Publication Date: 2019-04-09 Application Number: 15/863,983 Filing Date: 2018-01-08 Inventor: Huang, Chang-cheng   Liu shen iuan   Huang, Ju-lin   Tzeng, Tzu-chien   Liang, Keko-chun   Wang, Yu-hsiang   Yeh, Che-wei   Assignee: Novatek Microelectronics Corp.   IPC: H04L7/00 Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.
7
US2019113939A1
REFERENCE VOLTAGE GENERATOR
Publication/Patent Number: US2019113939A1 Publication Date: 2019-04-18 Application Number: 16/052,654 Filing Date: 2018-08-02 Inventor: Fang, Yong-ren   Liu shen iuan   Huang, Ju-lin   Tzeng, Tzu-chien   Liang, Keko-chun   Wang, Yu-hsiang   Yeh, Che-wei   Assignee: Novatek Microelectronics Corp.   IPC: G05F1/46 Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.
8
US2018198597A1
CLOCK AND DATA RECOVERY CIRCUIT WITH JITTER TOLERANCE ENHANCEMENT
Publication/Patent Number: US2018198597A1 Publication Date: 2018-07-12 Application Number: 15/863,983 Filing Date: 2018-01-08 Inventor: Yeh, Che-wei   Wang, Yu-hsiang   Liang, Keko-chun   Tzeng, Tzu-chien   Huang, Ju-lin   Liu shen iuan   Huang, Chang-cheng   Assignee: Novatek Microelectronics Corp.   IPC: H03L7/091 Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.
9
TW201620255A
BANG-BANG PHASE LOCK LOOP
Publication/Patent Number: TW201620255A Publication Date: 2016-06-01 Application Number: 103140614 Filing Date: 2014-11-24 Inventor: Liu, Shen Iuan   Kuan, Ting Kuei   Assignee: National Taiwan University   IPC: H03L7/08 Abstract: A bang-bang phase lock loop (BBPLL) is proposed. The BBPLL includes a bang-bang phase frequency detector (BBPFD)
10
TWI521859B
OSCILLATOR
Publication/Patent Number: TWI521859B Publication Date: 2016-02-11 Application Number: 103101617 Filing Date: 2014-01-16 Inventor: Liu, Shen Iuan   Chiang, Yu Hsuan   Assignee: National Taiwan University   IPC: H03B5/04 Abstract: A oscillator with temperature compensation and no resistance is provided. In this disclosure
11
TWI527380B
APPARATUS FOR FREQUENCY LOCKING
Publication/Patent Number: TWI527380B Publication Date: 2016-03-21 Application Number: 103101774 Filing Date: 2014-01-17 Inventor: Liu, Shen Iuan   Tseng, Kai Hui   Assignee: National Taiwan University   IPC: H03L7/06 Abstract: An apparatus for frequency locking is provided. The apparatus includes a pulse generator
12
TWI539754B
BANG-BANG PHASE LOCK LOOP
Publication/Patent Number: TWI539754B Publication Date: 2016-06-21 Application Number: 103140614 Filing Date: 2014-11-24 Inventor: Liu, Shen Iuan   Kuan, Ting Kuei   Assignee: National Taiwan University   IPC: H03L7/08 Abstract: A bang-bang phase lock loop (BBPLL) is proposed. The BBPLL includes a bang-bang phase frequency detector (BBPFD)
13
TWI524676B
All digital phase-locked loops and operating method thereof
Publication/Patent Number: TWI524676B Publication Date: 2016-03-01 Application Number: 101142348 Filing Date: 2012-11-14 Inventor: Liu, Shen Iuan   Zeng, Kai-hui   Assignee: National Taiwan University   IPC: H03L7/085 Abstract: The present invention discloses an all digital phase-locked loops and operating method thereof. The all digital phase-locked loops comprises a bang-bang phase detector
14
TW201624926A
Pulse calibration circuit
Publication/Patent Number: TW201624926A Publication Date: 2016-07-01 Application Number: 103144754 Filing Date: 2014-12-22 Inventor: Liu shen iuan   Wei, Chih-lu   Assignee: National Taiwan University   IPC: H03K5/14 Abstract: A pulse calibration circuit is proposed. The pulse calibration circuit includes a pulse injection timing point calibration circuit and a pulse width calibration circuit. The pulse injection timing point calibration circuit calibrates a reference clock signal to generate a calibrated clock signal according to a mode signal and a first clock signal from a voltage controlled oscillator (VCO). The pulse width calibration circuit receives a ratio control signal and the calibrated clock signal and accordingly generates an injection pulse. The pulse injection timing point calibration circuit generates an activation signal according to the mode signal
15
TWI538411B
Injection-locked phase-locked loop
Publication/Patent Number: TWI538411B Publication Date: 2016-06-11 Application Number: 104111079 Filing Date: 2015-04-07 Inventor: Liu shen iuan   Yeh, Che-wei   Assignee: National Taiwan University   IPC: H03L7/099 Abstract: An injection-locked phase-locked loop is provided. The injection-locked phase-locked loop includes a signal generation unit receiving an input signal to generate an injection signal and a reference signal according to the input signal
16
TW201637367A
Injection-locked phase-locked loop
Publication/Patent Number: TW201637367A Publication Date: 2016-10-16 Application Number: 104111079 Filing Date: 2015-04-07 Inventor: Liu shen iuan   Yeh, Che-wei   Assignee: National Taiwan University   IPC: H03L7/099 Abstract: An injection-locked phase-locked loop is provided. The injection-locked phase-locked loop includes a signal generation unit receiving an input signal to generate an injection signal and a reference signal according to the input signal
17
TWI538410B
Pulse calibration circuit
Publication/Patent Number: TWI538410B Publication Date: 2016-06-11 Application Number: 103144754 Filing Date: 2014-12-22 Inventor: Liu shen iuan   Wei, Chih-lu   Assignee: National Taiwan University   IPC: H03K5/14 Abstract: A pulse calibration circuit is proposed. The pulse calibration circuit includes a pulse injection timing point calibration circuit and a pulse width calibration circuit. The pulse injection timing point calibration circuit calibrates a reference clock signal to generate a calibrated clock signal according to a mode signal and a first clock signal from a voltage controlled oscillator (VCO). The pulse width calibration circuit receives a ratio control signal and the calibrated clock signal and accordingly generates an injection pulse. The pulse injection timing point calibration circuit generates an activation signal according to the mode signal
18
TWI505647B
Frequency synthesizer and frequency synthesizing method thereof
Publication/Patent Number: TWI505647B Publication Date: 2015-10-21 Application Number: 99142834 Filing Date: 2010-12-08 Inventor: Liu, Shen Iuan   Lee, I Ting   Assignee: National Taiwan University   IPC: H03L7/18 Abstract: A frequency synthesizer and frequency synthesizing method thereof is provided. The frequency synthesizer includes a sigma delta modulator
19
TW201501472A
Multiplying delay lock loop
Publication/Patent Number: TW201501472A Publication Date: 2015-01-01 Application Number: 102121759 Filing Date: 2013-06-19 Inventor: Liu, Shen Iuan   Chen, Sheng Tzung   Assignee: National Taiwan University   IPC: H03K5/14 Abstract: A multiplying delay lock loop is provided. Determine a time point of injecting an input reference clock signal according to a start signal and an ending signal generated by delaying a first reference clock signal.
20
TW201524115A
Temperature compensation circuit and current source circuit for reducing temperature coefficient
Publication/Patent Number: TW201524115A Publication Date: 2015-06-16 Application Number: 102146286 Filing Date: 2013-12-13 Inventor: Liu, Shen Iuan   Chiang, Yu Hsuan   Assignee: National Taiwan University   IPC: H03F1/30 Abstract: A current source with low temperature coefficient includes a first transistor
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