Country
Full text data for US,EP,CN
Type
Legal Validity
Legal Status
Filing Date
Publication Date
Inventor
Assignee
Click to expand
IPC(Section)
IPC(Class)
IPC(Subclass)
IPC(Group)
IPC(Subgroup)
Agent
Agency
Claims Number
Figures Number
Citation Number of Times
Assignee Number
No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
Application Number Application Number Filing Date Filing Date
Inventor Inventor Assignee Assignee IPC IPC
1
US10468541B2
Semiconductor device with through-substrate via and corresponding method of manufacture
Publication/Patent Number: US10468541B2 Publication Date: 2019-11-05 Application Number: 15/107,901 Filing Date: 2014-12-12 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Loeffler, Bernhard   Holzhaider, Rainer   Assignee: ams AG   IPC: H01L31/0224 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.
2
US10062610B2
Method of producing an opening with smooth vertical sidewall in a semiconductor substrate
Publication/Patent Number: US10062610B2 Publication Date: 2018-08-28 Application Number: 15/520,821 Filing Date: 2015-10-15 Inventor: Koppitsch, Guenther   Loeffler, Bernhard   Assignee: ams AG   IPC: H01L21/00 Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.
3
US2017316976A1
METHOD OF PRODUCING AN OPENING WITH SMOOTH VERTICAL SIDEWALL IN A SEMICONDUCTOR SUBSTRATE
Publication/Patent Number: US2017316976A1 Publication Date: 2017-11-02 Application Number: 15/520,821 Filing Date: 2015-10-15 Inventor: Koppitsch, Guenther   Loeffler, Bernhard   Assignee: ams AG   IPC: H01L21/768 Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.
4
US2016322519A1
SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA AND CORRESPONDING METHOD OF MANUFACTURE
Publication/Patent Number: US2016322519A1 Publication Date: 2016-11-03 Application Number: 15/107,901 Filing Date: 2014-12-12 Inventor: Schrank, Franz   Carniello, Sara   Enichlmair, Hubert   Kraft, Jochen   Loeffler, Bernhard   Holzhaider, Rainer   Assignee: AMS AG   IPC: H01L31/0224 Abstract: A dielectric layer (2) is arranged on the main surface (10) of a semiconductor substrate (1), and a passivation layer (6) is arranged on the dielectric layer. A metal layer (3) is embedded in the dielectric layer above an opening (12) in the substrate, and a metallization (14) is arranged in the opening. The metallization contacts the metal layer and forms a through-substrate via to a rear surface (11) of the substrate. A layer or layer sequence (7, 8, 9) comprising at least one further layer is arranged on the passivation layer above the opening. In this way the bottom of the through-substrate via is stabilized. A plug (17) may additionally be arranged in the opening without filling the opening.
5
US2014349462A1
Method for producing thin semiconductor components
Publication/Patent Number: US2014349462A1 Publication Date: 2014-11-27 Application Number: 20/121,435 Filing Date: 2012-09-18 Inventor: Loeffler, Bernhard   Siegert, Joerg   Stering, Bernhard   Assignee: ams AG   AMS AG   IPC: H01L21/683 Abstract: A semiconductor substrate (1) is provided with a structure (3) on an upper side (2)
6
DE102011116409B3
Verfahren zur Herstellung dünner Halbleiterbauelemente
Title (English): The claimant states that:
Publication/Patent Number: DE102011116409B3 Publication Date: 2013-03-07 Application Number: 102011116409 Filing Date: 2011-10-19 Inventor: Loeffler, Bernhard   Siegert, Joerg   Stering, Bernhard   Assignee: Austriamicrosystems AG   IPC: H01L21/304 Abstract: Ein Halbleitersubstrat (1) wird an einer Oberseite (2) mit einer Struktur (3) versehen
7
WO2013056936A1
METHOD FOR PRODUCING THIN SEMICONDUCTOR COMPONENTS
Publication/Patent Number: WO2013056936A1 Publication Date: 2013-04-25 Application Number: 2012068344 Filing Date: 2012-09-18 Inventor: Loeffler, Bernhard   Siegert, Joerg   Stering, Bernhard   Assignee: LOEFFLER, BERNHARD   SIEGERT, JOERG   AMS AG   STERING, BERNHARD   IPC: H01L21/683 Abstract: The invention relates to a semiconductor substrate (1) having a structure (3) on an upper face (2) and another substrate (4) for handling the semiconductor substrate which is likewise structured on an upper face (5). The structuring of the other substrate occurs in at least partial correspondence to the structure of the semiconductor substrate. The structured upper faces of the semiconductor substrate and the other substrate face each other and are permanently connected to each other. The semiconductor substrate is then thinned from the rear face (6) and the other substrate is removed at least far enough so that the structure of the semiconductor substrate is exposed to a sufficient extent for further use.
8
WO2012031845A1
METHOD FOR PRODUCING A SEMICONDUCTOR COMPONENT WITH A THROUGH-CONTACT AND SEMICONDUCTOR COMPONENT WITH THROUGH-CONTACT
Publication/Patent Number: WO2012031845A1 Publication Date: 2012-03-15 Application Number: 2011063709 Filing Date: 2011-08-09 Inventor: Schrank, Franz   Kraft, Jochen   Koppitsch, Guenther   Loeffler, Bernhard   Teva, Jordi   Jessenig, Stefan   Siegert, Joerg   Assignee: Austriamicrosystems AG   SCHRANK, FRANZ   KRAFT, JOCHEN   KOPPITSCH, GUENTHER   LOEFFLER, BERNHARD   TEVA, JORDI   JESSENIG, STEFAN   SIEGERT, JOERG   IPC: H01L21/768 Abstract: Through the intermetal dielectric (2) and the semiconductor material of the substrate (1) a contact hole is formed
9
DE102010045055A1
Verfahren zur Herstellung eines Halbleiterbauelementes mit einer Durchkontaktierung und Halbleiterbauelement mit Durchkontaktierung
Title (English): The claimant also alleges that, in the United States and Regulation No. 4,
Publication/Patent Number: DE102010045055A1 Publication Date: 2012-03-15 Application Number: 102010045055 Filing Date: 2010-09-10 Inventor: Schrank, Franz   Loeffler, Bernhard   Koppitsch, Guenther Dr   Kraft, Jochen Dr   Teva, Jordi   Jessenig, Stefan   Siegert, Joerg Dr   Assignee: Austriamicrosystems AG   IPC: H01L21/283 Abstract: Verfahren zur Herstellung eines Halbleiterbauelementes mit einer Durchkontaktierung und Halbleiterbauelement mit Durchkontaktierung Durch das Zwischenmetalldielektrikum (2) und das Halbleitermaterial des Substrates (1) hindurch wird ein Kontaktloch (6) gebildet
10
US8063458B2
Micromechanical component, method for fabrication and use
Publication/Patent Number: US8063458B2 Publication Date: 2011-11-22 Application Number: 11/918,189 Filing Date: 2006-03-28 Inventor: Loeffler, Bernhard   Schrank, Franz   Assignee: austriamicrosystems AG   IPC: H01L29/84 Abstract: A micromechanical component that can be produced in an integrated thin-film method is disclosed, which component can be produced and patterned on the surface of a substrate as multilayer construction. At least two metal layers that are separated from the substrate and with respect to one another by interlayers are provided for the multilayer construction. Electrically conductive connecting structures provide for an electrical contact of the metal layers among one another and with a circuit arrangement arranged in the substrate. The freely vibrating membrane that can be used for an inertia sensor, a microphone or an electrostatic switch can be provided with matching and passivation layers on all surfaces in order to improve its mechanical properties, said layers being concomitantly deposited and patterned during the layer producing process or during the construction of the multilayer construction. Titanium nitride layers are advantageously used for this.
11
DE102006012447B4
Verfahren zur Herstellung einer Transistorstruktur
Title (English): Methods of manufacturing transient structures.
Publication/Patent Number: DE102006012447B4 Publication Date: 2011-07-28 Application Number: 102006012447 Filing Date: 2006-03-17 Inventor: Roehrer, Georg   Loeffler, Bernhard   Kraft, Jochen Dr   Assignee: Austriamicrosystems AG   IPC: H01L21/331 Abstract: Verfahren zur Herstellung einer Transistorstruktur (10)
12
US2011117714A1
Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation
Publication/Patent Number: US2011117714A1 Publication Date: 2011-05-19 Application Number: 12/622,028 Filing Date: 2009-11-19 Inventor: Levy, Max   Feilchenfeld, Natalie   Phelps, Richard   Rainey, Bethann   Slinkman, James   Voldman, Steven H.   Zierak, Michael   Enichlmair, Hubert   Knaipp, Martin   Loeffler, Bernhard   Minixhofer, Rainer   Park, Jong-mun   Roehrer, Georg   Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION   IPC: H01L21/762 Abstract: A method of forming an isolation region is provided that in one embodiment substantially reduces divot formation. In one embodiment, the method includes providing a semiconductor substrate, forming a first pad dielectric layer on an upper surface of the semiconductor substrate and forming a trench through the first pad dielectric layer into the semiconductor substrate. In a following process sequence, the first pad dielectric layer is laterally etched to expose an upper surface of the semiconductor substrate that is adjacent the trench, and the trench is filled with a trench dielectric material, wherein the trench dielectric material extends atop the upper surface of the semiconductor substrate adjacent the trench and abuts the pad dielectric layer.
13
US2009014819A1
Micromechanical Component, Method for Fabrication and Use
Publication/Patent Number: US2009014819A1 Publication Date: 2009-01-15 Application Number: 11/918,189 Filing Date: 2006-03-28 Inventor: Loeffler, Bernhard   Schrank, Franz   Assignee: Loeffler, Bernhard   Schrank, Franz   IPC: H01L29/84 Abstract: A micromechanical component that can be produced in an integrated thin-film method is disclosed, which component can be produced and patterned on the surface of a substrate as multilayer construction. At least two metal layers that are separated from the substrate and with respect to one another by interlayers are provided for the multilayer construction. Electrically conductive connecting structures provide for an electrical contact of the metal layers among one another and with a circuit arrangement arranged in the substrate. The freely vibrating membrane that can be used for an inertia sensor, a microphone or an electrostatic switch can be provided with matching and passivation layers on all surfaces in order to improve its mechanical properties, said layers being concomitantly deposited and patterned during the layer producing process or during the construction of the multilayer construction. Titanium nitride layers are advantageously used for this.
14
DE102007052820A1
Method for producing isolation trench in semiconductor substrate
Publication/Patent Number: DE102007052820A1 Publication Date: 2009-05-14 Application Number: 102007052820 Filing Date: 2007-11-06 Inventor: Loeffler, Bernhard   Wachmann, Ewald   Assignee: Austriamicrosystems AG   IPC: H01L21/764 Abstract: The method involves etching a trench in a substrate (1) at an upper side of the substrate made of a semiconductor material. The existing surfaces of the substrate are covered with a protective layer in the trench. An epitaxial layer is formed on the upper side of the substrate by epitaxial growth of semiconductor material. Thermal oxidation is carried out on the epitaxial layer
15
US7629628B2
Bipolar transistor including a base layer containing carbon atoms and having three distinct layers being doped with a trivalent substance
Publication/Patent Number: US7629628B2 Publication Date: 2009-12-08 Application Number: 10/500,079 Filing Date: 2002-12-20 Inventor: Kraft, Jochen   Loeffler, Bernhard   Roehrer, Georg   Assignee: Austriamicrosystems AG   IPC: H01L29/737 Abstract: A transistor includes an emitter, a collector, and a base layer having a base contact. The base layer includes an intrinsic region between the emitter and the collector, an extrinsic region between the intrinsic region and the base contact, and a first doping layer that is doped with a trivalent substance, that extends into the extrinsic region, and that is counter-doped with a pentavalent substance in a region adjacent to the emitter.
16
DE102005025937B4
Lichtempfindliches Bauelement mit erhöhter Blauempfindlichkeit
Title (English): Photosensitive components with high blue sensitivity
Publication/Patent Number: DE102005025937B4 Publication Date: 2009-11-26 Application Number: 102005025937 Filing Date: 2005-06-06 Inventor: Kraft, Jochen   Enichlmair, Hubert   Roehrer, Georg   Loeffler, Bernhard   Meinhardt, Gerald   Wachmann, Ewald   Assignee: Austriamicrosystems AG   IPC: H01L31/11 Abstract: Es wird ein lichtempfindliches Bauelement vorgeschlagen
17
DE102005027456B4
Photodiode mit verringertem Dunkelstrom
Title (English): Photodiode with reduced undercurrent
Publication/Patent Number: DE102005027456B4 Publication Date: 2008-10-16 Application Number: 102005027456 Filing Date: 2005-06-14 Inventor: Kraft, Jochen   Loeffler, Bernhard   Meinhardt, Gerald   Assignee: Austriamicrosystems AG   IPC: H01L21/328 Abstract: Es wird eine Photodiode vorgeschlagen
18
DE10164176B4
Bipolartransistor
Title (English): Double tube
Publication/Patent Number: DE10164176B4 Publication Date: 2007-12-27 Application Number: 10164176 Filing Date: 2001-12-27 Inventor: Kraft, Jochen   Roehrer, Georg   Loeffler, Bernhard   Assignee: Austriamicrosystems AG   IPC: H01L21/331 Abstract: The invention relates to a transistor comprising an emitter (1)
19
DE102006012447A1
Verfahren zur Herstellung einer Transistorstruktur
Title (English): Methods of manufacturing transient structures.
Publication/Patent Number: DE102006012447A1 Publication Date: 2007-09-20 Application Number: 102006012447 Filing Date: 2006-03-17 Inventor: Roehrer, Georg   Loeffler, Bernhard   Kraft, Jochen Dr   Assignee: Austriamicrosystems AG   IPC: H01L21/331 Abstract: Verfahren zur Herstellung einer Transistorstruktur (10)
20
DE102004054806A1
Bipolar transistor has intrinsic base region with an electronically conductive silicide layer in close contact with base layer
Publication/Patent Number: DE102004054806A1 Publication Date: 2006-05-24 Application Number: 102004054806 Filing Date: 2004-11-12 Inventor: Enichlmair, Hubert   Loeffler, Bernhard   Assignee: AUSTRIAMICROSYSTEMS AG, UNTERPREMSTAETTEN   IPC: H01L21/331 Abstract: Bipolar transistor comprises a collector (KG) and emitter (E) supported by a base layer (BS) forming an intrinsic base region with an electronically conductive silicide layer (SS) outside the base region in close contact with the base layer and together with it forming a low-resistance extrinsic base. An independent claim is also included for a production process for the above.
Total 3 pages