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No. Publication Number Title Publication/Patent Number Publication/Patent Number Publication Date Publication Date
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1
US10957664B2
Semiconductor structure and manufacturing method thereof
Publication/Patent Number: US10957664B2 Publication Date: 2021-03-23 Application Number: 16/425,538 Filing Date: 2019-05-29 Inventor: Wu, Tung-jiun   Chang, Mingni   Wang, Ming-yih   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L23/00 Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.
2
US2020402924A1
SEMICONDUCTOR STRUCTURE
Publication/Patent Number: US2020402924A1 Publication Date: 2020-12-24 Application Number: 16/921,850 Filing Date: 2020-07-06 Inventor: Wu, Tung-jiun   Lu, Yinlung   Chang, Mingni   Wang, Ming-yih   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L23/00 Abstract: A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.
3
US10707179B1
Semiconductor structure and method for forming the same
Publication/Patent Number: US10707179B1 Publication Date: 2020-07-07 Application Number: 16/450,536 Filing Date: 2019-06-24 Inventor: Wu, Tung-jiun   Lu, Yinlung   Chang, Mingni   Wang, Ming-yih   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L21/00 Abstract: A semiconductor structure including a MIM capacitor includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad.
4
US2020381378A1
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
Publication/Patent Number: US2020381378A1 Publication Date: 2020-12-03 Application Number: 16/425,538 Filing Date: 2019-05-29 Inventor: Wu, Tung-jiun   Chang, Mingni   Wang, Ming-yih   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: H01L23/00 Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.
5
US2020064396A1
METHOD AND SYSTEM FOR WAFER-LEVEL TESTING
Publication/Patent Number: US2020064396A1 Publication Date: 2020-02-27 Application Number: 16/522,551 Filing Date: 2019-07-25 Inventor: He, Jun   Lin, Yu-ting   Lin, Wei-hsun   Kuo, Yung-liang   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: G01R31/28 Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
6
US10726191B2
Method and system for manufacturing a semiconductor device
Publication/Patent Number: US10726191B2 Publication Date: 2020-07-28 Application Number: 16/245,975 Filing Date: 2019-01-11 Inventor: Huang, Hsuan-ming   Teng, An Shun   Chang, Mingni   Wang, Ming-yih   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: G06F30/30 Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a capacitance difference between capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.
7
US2020104456A1
METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020104456A1 Publication Date: 2020-04-02 Application Number: 16/245,975 Filing Date: 2019-01-11 Inventor: Huang, Hsuan-ming   Teng, An Shun   Chang, Mingni   Wang, Ming-yih   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: G06F17/50 Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a difference in capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.
8
US2020356719A1
METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR DEVICE
Publication/Patent Number: US2020356719A1 Publication Date: 2020-11-12 Application Number: 16/940,256 Filing Date: 2020-07-27 Inventor: Huang, Hsuan-ming   Teng, An Shun   Chang, Mingni   Wang, Ming-yih   Lu, Yinlung   Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.   IPC: G06F30/398 Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes receiving a layout data representing information for manufacturing the semiconductor structure having a metal layer over a substrate. A first parasitic capacitance and a second parasitic capacitance are formed between the metal layer and the substrate. The method further includes determining a parasitic capacitance difference between a first region and a second region. The method further includes forming a dummy capacitor to minimize the parasitic capacitance difference. A system for manufacturing a semiconductor device is also provided.